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this is information on a product in full production. january 2013 doc id 023353 rev 5 1/133 1 stm32f302xb stm32f302xc stm32f303xb stm32f303xc arm cortex-m4f 32b mcu+fpu, up to 256kb flash+48kb sram 4 adcs, 2 dac ch., 7 comp, 4 pg a, timers, 2.0-3.6 v operation datasheet ? production data features core: arm? 32-bit cortex ? -m4f cpu (72 mhz max), single-cycle multiplication and hw division, dsp instruction with fpu (floating-point unit) and mpu (memory protection unit). operating conditions: ?v dd , v dda voltage range: 2.0 v to 3.6 v memories ? 128 to 256 kbytes of flash memory ? up to 40 kbytes of sram on data bus with hw parity check ? 8 kbytes of sram on instruction bus with hw parity check (ccm) crc calculation unit reset and supply management ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x 16 pll option ? internal 40 khz oscillator up to 87 fast i/os ? all mappable on external interrupt vectors ? several 5 v-tolerant 12-channel dma controller up to four adc 0.20 s (up to 39 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, separate analog supply from 2 to 3.6 v up to two 12-bit dac channels with analog supply from 2.4 to 3.6 v seven fast rail-to-rail analog comparators with analog supply from 2 to 3.6 v up to four operational amplifiers that can be used in pga mode, all terminal accessible with analog supply from 2.4 to 3.6 v up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors up to 13 timers ? one 32-bit timer and two 16-bit timers with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? up to two 16-bit 6-channel advanced-control timers, with up to 6 pwm channels, deadtime generation and emergency stop ? one 16-bit timer with 2 ic/ocs, 1 ocn/pwm, deadtime generation and emergency stop ? two 16-bit timers with ic/oc/ocn/pwm, deadtime generation and emergency stop ? two watchdog timers (independent, window) ? systick timer: 24-bit downcounter ? up to two 16-bit basic timers to drive the dac calendar rtc with alarm, periodic wakeup from stop/standby communication interfaces ? can interface (2.0b active) ?two i 2 c fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, wakeup from stop ? up to five usart/uarts (iso 7816 interface, lin, irda, modem control) ? up to three spis, two with multiplexed i 2 s interface, 4 to 16 programmable bit frame ? usb 2.0 full speed interface ? infrared transmitter serial wire debug, jtag, cortex-m4f etm 96-bit unique id table 1. device summary reference part number stm32f302xx stm32f302cb, stm32f302cc, stm32f302rb, stm32f302rc, STM32F302VB, stm32f302vc stm32f303xx stm32f303cb, stm32f303cc, stm32f303rb, stm32f303rc, stm32f303vb, stm32f303vc lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp48 (7 7 mm) www.st.com http://
contents stm32f302xx/stm32f303xx 2/133 doc id 023353 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm ? cortex?-m4f core with embedded flash and sram . . . . . . . . . 13 3.2 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 19 3.12 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.4 opamp reference voltage (vopamp) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.1 advanced timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) . . 24 3.16.3 basic timers (tim6, tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 http://
stm32f302xx/stm32f303xx contents doc id 023353 rev 5 3/133 3.16.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25 3.18 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19 universal synchronous/asynchronous receiver transmitter (usart) . . . 27 3.20 universal asynchronous receiver transmitte r (uart) . . . . . . . . . . . . . . . 27 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) . 28 3.22 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.23 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.24 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.25 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.26.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.26.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 59 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 59 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 http://
contents stm32f302xx/stm32f303xx 4/133 doc id 023353 rev 5 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.16 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.18 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.21 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 127 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 http://
stm32f302xx/stm32f303xx list of tables doc id 023353 rev 5 5/133 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f30xb/c family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. stm32f30xb/c i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. stm32f30xb/c spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. capacitive sensing gpios available on st m32f302xx/stm32f303xx devices . . . . . . . . 29 table 9. no. of capacitive sensing channels available on stm32f302xx/stm32f303xx devices . 30 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. stm32f302xx/stm32f303xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. alternate functions for port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13. alternate functions for port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 14. alternate functions for port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15. alternate functions for port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 16. alternate functions for port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 17. alternate functions for port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. stm32f30xb/c memory map and peripheral register boundary addresses . . . . . . . . . . . 51 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 24. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 25. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 table 27. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 28. typical and maximum current consumption from v dd supply at v dd = 3.6v . . . . . . . . . . . 62 table 29. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 63 table 30. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 65 table 31. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 65 table 32. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 66 table 33. typical current consumption in run mode, code with data processi ng running from flash 67 table 34. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 68 table 35. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 37. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 42. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 44. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 45. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 46. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 47. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 48. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 http://
list of tables stm32f302xx/stm32f303xx 6/133 doc id 023353 rev 5 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 51. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 53. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 56. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 57. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 58. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 59. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 60. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 61. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 62. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 63. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 65. usb: full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 table 66. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 67. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 68. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 table 69. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 70. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 71. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 72. operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 73. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 74. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 75. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 76. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 120 table 77. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 122 table 78. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 124 table 79. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 80. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 81. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 http://
stm32f302xx/stm32f303xx list of figures doc id 023353 rev 5 7/133 list of figures figure 1. stm32f302xb/stm32f302xc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. stm32f303xb/stm32f303xc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. stm32f302xx/stm32f303xx lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. stm32f302xx/stm32f303xx lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. stm32f302xx/stm32f303xx lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. stm32f30xb/c memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 12. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 66 figure 14. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 18. hsi oscillator accuracy characte rization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 19. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 20. tc and tta i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 21. five volt tolerant (ft and ftf) i/o input characteristics - cmos port. . . . . . . . . . . . . . . . . 88 figure 22. five volt tolerant (ft and ftf) i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . 89 figure 23. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 24. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 25. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 26. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 27. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 28. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 29. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 30. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 31. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 32. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 33. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 34. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 35. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 120 figure 36. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 37. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 122 figure 38. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 39. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 124 figure 40. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 http://
introduction stm32f302xx/stm32f303xx 8/133 doc id 023353 rev 5 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f30xb/c microcontrollers. this stm32f30xb/c datasheet should be read in conjunction with the stm32f30xb/c reference manual. the reference manual is available from the stmicroelectronics website www.st.com. for information on the cortex?-m4f core please refer to: cortex?-m4f technical reference manual , available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.cortexm.m4/ index.html stm32f3xxx and stm32f4xxx cortex-m4 programming manual (pm0214) available from the www.st.com website at the following address: http://www.st.com/internet /com/technical_resources/ technical_literature/progr amming_manual/dm00046982.pdf http://
stm32f302xx/stm32f303xx description doc id 023353 rev 5 9/133 2 description the stm32f302xx/stm32f303xx family is based on the high-performance arm ? cortex?-m4f 32-bit risc core operating at a frequency of up to 72 mhz, and embedding a floating point unit (fpu), a memory protection unit (mpu) and an embedded trace macrocell (etm). the family incorporates high-speed embedded memories (up to 256 kbytes of flash memory, up to 48 kbytes of sram) and an extensive range of enhanced i/os and peripherals connected to two apb buses. the devices offer up to four fast 12-bit adcs (5 msps), up to seven comparators, up to four operational amplifiers, up to two dac channels, a low-power rtc, up to five general- purpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. they also feature standard and advanced communication interfaces: up to two i 2 cs, up to three spis (two spis are with multiplexed full-duplex i2ss on stm32f303xb/stm32f303xc devices), three usarts, up to two uarts, can and usb. to achieve audio class accuracy, the i2s peripherals can be clocked via an external pll. the stm32f302xx/stm32f303xx family operates in the -40 to +85 c and -40 to +105 c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f302xx/stm32f303xx family offers devices in three packages ranging from 48 pins to 100 pins. the set of included peripherals changes with the device chosen. http://
description stm32f302xx/stm32f303xx 10/133 doc id 023353 rev 5 table 2. stm32f30xb/c family device features and peripheral counts peripheral stm32f 302cx stm32f 302rx stm32f 302vx stm32f 303cx stm32f 303rx stm32f 303vx flash (kbytes) 128 256 128 256 128 256 128 256 128 256 128 256 sram (kbytes) on data bus 24 32 24 32 24 32 32 40 32 40 32 40 sram (kbytes) on instruction bus (ccm: core coupled memory) 8 timers advanced control 1 (16-bit) 2 (16-bit) general purpose 5 (16-bit) 1 (32-bit) basic 1 (16-bit) 2 (16-bit) comm. interfaces spi(i2s) (1) 33(2) i 2 c2 usart 3 uart 0 2 0 2 can 1 usb 1 gpios normal i/os (tc, tta) 20 27 45 20 27 45 5 volts to l e r a n t i/os (ft, ftf) 17 25 42 17 25 42 dma channels 12 capacitive sensing channels 17 18 24 17 18 24 12-bit adcs 2 4 12-bit dac channels 1 2 analog comparator 4 7 operational amplifiers 2 4 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: - 40 to 85 c / - 40 to 105 c junction temperature: - 40 to 125 c packages lqfp48 lqfp64 lqf p100 lqfp48 lqfp64 lqfp100 1. in stm32f303xb/stm32f303xc devices the spi interfaces can work in an exclusive way in either the spi mode or the i 2 s audio mode. http://
stm32f302xx/stm32f303xx description doc id 023353 rev 5 11/133 figure 1. stm32f302xb/stm32f302xc block diagram 1. af: alternate function on i/o pins. ms18959v5 touch sensing controller ahb decoder timer 16 2 channels,1 comp channel, brk as af timer 17 timer 1 / pwm spi1 mosi, miso, sck,nss as af usart1 rx, tx, cts, rts, smartcard as af winwatchdog busmatrix mpu/fpu cortex m4 cpu f max : 72 mhz nvic gp dma1 7 channels ccm ram 8kb flash interface obl flash 256 kb 64 bits jtrst jtdi jtck/swclk jtms/swdio jtdo as af power voltage reg. 3.3 v to 1.8v v dd18 supply supervision por /pdr pvd por reset int. v ddio = 2 to 3.6 v v ss nreset v dda v ssa ind. wdg32k standby interface pll @v ddio @v dda xtal osc 4 -32 mhz reset & clock control ahbpclk apbp1clk apbp2clk ahb2 apb2 ahb2 apb1 crc apb1 f max = 36 mhz apb2 f max = 72 mhz gpio port a gpio port b gpio port c gpio port d gpio port e osc_in osc_out spi3 scl, sda, smba as af usart2 scl, sda, smba as af usart3 rc ls timer6 timer 4 spi2 12bit dac1 if @v dda timer2 (32-bit/pwm) pa[15:0] pb[15:0] pc[15:0] mosi, miso, sck, nss as af 4 channels, etr as af usb_dp, usb_dm dac1_ch1 as af hclk fclk usartclk rc hs 8mhz sram 40 kb etm trace/trig swjtag tpiu ibus tradeclk traced[0-3] as af dbus system gp dma2 5 channels 12-bit adc1 12-bit adc2 temp. sensor v ref+ v ref- timer 15 ext.it wkup xx af 1 channel, 1 comp channel, brk as af 1 channel, 1 comp channel, brk as af 4 channels, 4 comp channels, etr, brk as af gpio port f pd[15:0] pe[15:0] usb sram 512b pf[7:0] if i2cclk adc sar 1/2/3/4 clk @v ddio @v dda @vsw xtal 32khz osc32_in osc32_out v bat = 1.65v to 3.6v rtc awu backup reg (64byte) backup interface anti-tamp timer 3 uart4 uart5 i2c1 i2c2 bx can & 512b sram usb 2.0 fs opamp1 opamp2 @v dda inxx / outxx inxx / outxx interface syscfg ctl gp comparator 6 gp comparator 4 gp comparator 2 can tx, can rx 4 channels, etr as af 4 channels, etr as af rx, tx, cts, rts, as af rx, tx, cts, rts, as af rx, tx as af rx, tx as af @v dda xx ins, 4 outs as af xx groups of 4 channels as af mosi, miso, sck, nss as af gp comparator 1 http://
description stm32f302xx/stm32f303xx 12/133 doc id 023353 rev 5 figure 2. stm32f303xb/stm32f303xc block diagram 1. af: alternate function on i/o pins. ms18960v4 touch sensing controller timer 16 2 channels,1 comp channel, brk as af timer 17 timer 1 / pwm timer 8 / pwm 4 channels, 4 comp channels, etr, brk as af spi1 mosi, miso, sck,nss as af usart1 rx, tx, cts, rts, smartcard as af winwatchdog busmatrix mpu/fpu cortex m4 cpu f max : 72 mhz nvic gp dma1 7 channels ccm ram 8kb flash interface obl flash 256 kb 64 bits jtrst jtdi jtck/swclk jtms/swdio jtdo as af power voltage reg. 3.3 v to 1.8v v dd18 supply supervision por /pdr pvd por reset int. v ddio = 2 to 3.6 v v ss nreset v dda v ssa ind. wdg32k standby interface pll @v ddio @v dda xtal osc 4 -32 mhz reset & clock control ahbpclk apbp1clk apbp2clk ahb2 apb2 ahb2 apb1 crc apb1 f max = 36 mhz apb2 f max = 72 mhz gpio port a gpio port b gpio port c gpio port d gpio port e osc_in osc_out spi3/i2s scl, sda, smba as af usart2 scl, sda, smba as af usart3 rc ls timer6 timer 4 spi2/i2s 12bit dac1 if @v dda timer2 (32-bit/pwm) pa[15:0] pb[15:0] pc[15:0] mosi/sd, miso/ext_sd, sck/ck, nss/ws, mclk as af 4 channels, etr as af usb_dp, usb_dm dac1_ch1 as af hclk fclk usartclk rc hs 8mhz sram 40 kb etm trace/trig swjtag tpiu ibus tradeclk traced[0-3] as af dbus system gp dma2 5 channels 12-bit adc1 12-bit adc2 if temp. sensor v ref+ v ref- timer 15 ext.it wkup xx af 1 channel, 1 comp channel, brk as af 1 channel, 1 comp channel, brk as af 4 channels, 4 comp channels, etr, brk as af gpio port f pd[15:0] pe[15:0] timer7 usb sram 512b pf[7:0] 12-bit adc3 if 12-bit adc4 i2cclk adc sar 1/2/3/4 clk @v ddio @v dda @vsw xtal 32khz osc32_in osc32_out v bat = 1.65v to 3.6v rtc awu backup reg (64byte) backup interface anti-tamp timer 3 uart4 uart5 i2c1 i2c2 bx can & 512b sram usb 2.0 fs dac1_ch2 as af opamp1 opamp2 opamp3 opamp4 @v dda inxx / outxx inxx / outxx inxx / outxx inxx / outxx interface syscfg ctl gp comparator 7 p gp comparator... gp comparator 1 can tx, can rx 4 channels, etr as af 4 channels, etr as af mosi/sd, miso/ext_sd, sck/ck, nss/ws, mclk as af rx, tx, cts, rts, as af rx, tx, cts, rts, as af rx, tx as af rx, tx as af @v dda xx ins, 7 outs as af xx groups of 4 channels as af ahb2 ahb3 http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 13/133 3 functional overview 3.1 arm ? cortex?-m4f core with embedded flash and sram the arm cortex-m4f processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4f 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructi ons which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32f302xx/stm32f303xx family is compatible with all arm tools and software. figure 1 and figure 2 show the general block diagrams of the stm32f302xx/stm32f303xx family devices. 3.2 memory protection unit (mpu) the memory protection unit (mpu) is used to separate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically upd ate the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 3.3 embedded flash memory all stm32f302xx/stm32f303xx devices feature up to 256 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). http://
functional overview stm32f302xx/stm32f303xx 14/133 doc id 023353 rev 5 3.4 embedded sram stm32f302xx/stm32f303xx devices feature up to 48 kbytes of embedded sram with hardware parity check. the memory can be accessed in read/write at cpu clock speed with 0 wait states, allowing the cpu to achieve 90 dhrystone mips at 72 mhz (when running code from ccm, core coupled memory). 8 kbytes of sram mapped on the instruction bus (core coupled memory (ccm)), used to execute critical routines or to access data (parity check on all of ccm ram). 40 kbytes of sram mapped on the data bus (parity check on first 16 kbytes of sram). 3.5 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart2 (pd5/pd6) or usb (pa11/pa12) through dfu (device firmware upgrade) . 3.6 cyclic redundancy check (crc) the crc (cyclic redundancy check) calculatio n unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 15/133 3.7 power management 3.7.1 power supply schemes v ss , v dd = 2.0 to 3.6 v : external power supply for i/os and the internal regulator. it is provided externally through v dd pins v ssa , v dda = 2.0 to 3.6 v: external analog power supply for adc, dacs, comparators operational amplifiers, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the dacs and operational amplifiers are used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. v bat = 1.65 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.7.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.7.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr), and power-down. the mr mode is used in the nominal regulation mode (run) the lpr mode is used in stop mode. the power-down mode is used in standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. http://
functional overview stm32f302xx/stm32f303xx 16/133 doc id 023353 rev 5 3.7.4 low-power modes the stm32f302xx/stm32f303xx supports three low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the usb wakeup on stm32f303xb/stm32f303xc devices, the rtc alarm, compx, i2cx or u(s)artx. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin or an rtc alarm occurs. note: the rtc, the iwdg and the corresponding clock sources are not stopped by entering stop or standby mode. http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 17/133 3.8 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the hi gh speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz, while the maximum allowed fr equency of the low speed apb domain is 36 mhz. http://
functional overview stm32f302xx/stm32f303xx 18/133 doc id 023353 rev 5 figure 3. clock tree /32 4-32 mhz hse osc osc_in osc_out osc32_in osc32_out 8 mhz hsi rc iwdgclk to iwdg pll x2,x3,.. x16 pllmul mco main clock output ahb /2 pllclk hsi hse apb1 prescaler /1,2,4,8,16 hclk pllclk to ahb bus, core, memory and dma lse lsi hsi hsi hse to rtc pllsrc sw mco /8 sysclk rtcclk rtcsel[1:0] sysclk to tim 2,3,4,6,7 if (apb1 prescaler =1) x1 else x2 flitfclk to flash programming interface lsi to i2cx (x = 1,2) to u(s)artx (x = 2..5) lse hsi sysclk /2 pclk1 sysclk hsi pclk1 ms19989v4 to i2sx (x = 2,3) usbclk to usb interface to cortex system timer fhclk cortex free running clock to apb1 peripherals ahb prescaler /1,2,..512 css /2,/3,... /16 lse osc 32.768khz lsi rc 40khz usb prescaler /1,1.5 apb2 prescaler /1,2,4,8,16 to tim 15,16,17 if (apb2 prescaler =1) x1 else x2 to usart1 lse hsi sysclk pclk2 pclk2 to apb2 peripherals tim1/8 adc prescaler /1,2,4 to adcxy (xy = 12, 34) adc prescaler /1,2,4,6,8,10,12,16, 32,64,128,256 i2ssrc sysclk ext. clock i2s_ckin x2 http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 19/133 3.9 general-purpose input/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.10 direct memory access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each of the 12 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, dac and adc. 3.11 interrupts and events 3.11.1 nested vectored interrupt controller (nvic) the stm32f302xx/stm32f303xx devices embed a nested vectored interrupt controller (nvic) able to handle up to 66 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. http://
functional overview stm32f302xx/stm32f303xx 20/133 doc id 023353 rev 5 3.12 fast analog-to-digital converter (adc) up to four fast analog-to-digital converters 5 msps, with selectable resolution between 12 and 6 bit, are embedded in the stm32f302xx/stm32f303xx family devices. the adcs have up to 39 external channels. some of the external channels are shared between adc1&2 and between adc3&4, performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adcs have also internal channels: tem perature sensor connected to adc1 channel 16, v bat/2 connected to adc1 channel 17, voltage reference v refint connected to the 4 adcs channel 18, vopamp1 connected to adc1 channel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold single-shunt phase current reading techniques. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers and the advanced-control timers (tim1 on all devices and tim8 on stm32f303xb/stm32f303xc devices) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 3.12.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperat ure sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.12.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc_in18 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 21/133 3.12.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.12.4 opamp reference voltage (vopamp) every opamp reference voltage can be measured using a corresponding adc internal channel: vopamp1 connected to adc1 channel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. http://
functional overview stm32f302xx/stm32f303xx 22/133 doc id 023353 rev 5 3.13 digital-to-analog converter (dac) up to two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supports the following features: up to two dac output channels on stm32f303xb/stm32f303xc devices 8-bit or 10-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability on stm32f303xb/stm32f303xc devices noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions on stm32f303xb/stm32f303xc devices dma capability (for each channel on stm32f303xb/stm32f303xc devices) external triggers for conversion 3.14 operational amplifier (opamp) the stm32f302xx/stm32f303xx embeds up to four operational amplifiers with external or internal follower routing and pga capability (o r even amplifier and filter capability with external components). when an operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: 8.2 mhz bandwidth 0.5 ma output capability rail-to-rail input/output in pga mode, the gain can be programmed to be 2, 4, 8 or 16. 3.15 fast comparators (comp) the stm32f302xx/stm32f303xx devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. the reference voltage can be one of the following: external i/o dac output pin internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 26: embedded internal reference voltage on page 60 for the value and precision of the internal reference voltage. all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 23/133 3.16 timers and watchdogs the stm32f302xx/stm32f303xx includes up to two advanced control timers, up to 6 general-purpose timers, two basic timers, two watchdog timers and a systick timer. the table below compares the features of the advanced control, general purpose and basic timers. 3.16.1 advanced timers (tim1, tim8) the advanced-control timers (tim1 on all devices and tim8 on stm32f303xb/stm32f303xc devices) can each be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: input capture output compare pwm generation (edge or ce nter-aligned modes) with full modulation capability (0- 100%) one-pulse mode output table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced tim1, tim8 (on stm32f303xb /stm32f303x c devices only) 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o general- purpose tim15 16-bit up any integer between 1 and 65536 ye s 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 ye s 1 1 basic tim6, tim7 (on stm32f303xb /stm32f303x c devices only) 16-bit up any integer between 1 and 65536 ye s 0 n o http://
functional overview stm32f302xx/stm32f303xx 24/133 doc id 023353 rev 5 in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.16.2 using the same architecture, so the advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.16.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) there are up to six synchronizable general-purpose timers embedded in the stm32f302xx/stm32f303xx (see ta b l e 3 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. tim2, 3, and tim4 these are full-featured general-purpose timers: ? tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. these timers all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. they can work together, or with the other general- purpose timers via the timer link featur e for synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generation and support quadrature encoders. tim15, 16 and 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.16.3 basic timers (tim6, tim7) these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. 3.16.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 25/133 3.16.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. 3.16.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 3.17 real-time clock (rtc) and backup registers the rtc and the 16 backup registers are supplied through a switch that takes power from either the v dd supply when present or the v bat pin. the backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. it supports the following features: calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. automatic correction for 28, 29 (leap year), 30 and 31 days of the month. two programmable alarms with wake up fr om stop and standby mode capability. on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. digital calibration circuit wit h 1 ppm resolution, to compensate for quartz crystal inaccuracy. three anti-tamper detection pins with programmable filter. the mcu can be woken up from stopand standby modes on tamper event detection. timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: a 32.768 khz external crystal a resonator or oscillator the internal low-power rc oscillator (typical frequency of 40 khz) the high-speed external clock divided by 32. http://
functional overview stm32f302xx/stm32f303xx 26/133 doc id 023353 rev 5 3.18 inter-integrated circuit interface (i 2 c) up to two i 2 c bus interfaces can operate in multimaster and slave modes. they can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, they provide hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management. they also have a clock domain independent from the cpu clock, allowing the i2cx (x=1,2) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to ta b l e 5 for the features available in i2c1 and i2c2. table 4. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process disabled when wakeup from stop mode is enabled table 5. stm32f30xb/c i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x x independent clock x x smbus x x wakeup from stop x x http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 27/133 3.19 universal synchronous/asynchronous receiver transmitter (usart) the stm32f302xx/stm32f303xx devices have three embedded universal synchronous/asynchron ous receiver transmitters (u sart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbits/s. they provide hardware management of the cts and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have lin master/slave capability. the usart interfaces can be served by the dma controller. 3.20 universal asynchronous receiver transmitter (uart) the stm32f302xx/stm32f303xx devices have 2 embedded universal asynchronous receiver transmitters (uart4, and uart5). the uart interfaces support irda sir endec, multiprocessor communication mode and single-wire half-duplex communication mode. the uart interfaces can be served by the dma controller. refer to ta b l e 6 for the features available in all u(s)arts interfaces table 6. usart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 hardware flow control for modem x x x continuous communication using dma x x x x x multiprocessor communication x x x x x synchronous mode x x x smartcard mode x x x single-wire half-duplex communication x x x x x irda sir endec block x x x x x lin mode xxxxx dual clock domain and wakeup from stop mode x x x x x receiver timeout interrupt x x x x x modbus communication x x x x x auto baud rate detection x x x driver enable x x x 1. x = supported. http://
functional overview stm32f302xx/stm32f303xx 28/133 doc id 023353 rev 5 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. two standard i2s interfaces (multiplexed with spi2 and spi3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. they can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. refer to ta b l e 7 for the features available in spi1, spi2 and spi3. 3.22 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.23 universal serial bus (usb) the stm32f302xx/stm32f303xx devices embed an usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator) . the usb has a dedicated 512-bytes sram memory for data transmission and reception. 3.24 infrared transmitter the stm32f302xx/stm32f303xx devices provide an infrared transmitter solution. the solution is based on internal connections betw een tim16 and tim17 as shown in the figure below. table 7. stm32f30xb/c spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 spi3 hardware crc calculation x x x rx/tx fifo x x x nss pulse mode x x x i2s mode x x ti mode xxx http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 29/133 tim17 is used to provide the carrier frequency and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control signals, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming the two timers output compare channels. figure 4. infrared transmitter 3.25 touch sensing controller (tsc) the stm32f302xx/stm32f303xx devices provide a simple solution for adding capacitive sensing functionality to any application. these devices offer up to 24 capacitive sensing channels distributed over 8 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. to limit the cpu bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. timer 16 (for envelop) timer 17 (for carrier) oc oc pb9/pa13 ms30365v1 table 8. capacitive sensing gpios available on stm32f302xx/stm32f303xx devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb11 tsc_g2_io2 pa5 tsc_g6_io2 pb12 tsc_g2_io3 pa6 tsc_g6_io3 pb13 tsc_g2_io4 pa7 tsc_g6_io4 pb14 http://
functional overview stm32f302xx/stm32f303xx 30/133 doc id 023353 rev 5 3.26 development support 3.26.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.26.2 embedded trace macrocell? the arm embedded trace macrocell provides a great er visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the 3 tsc_g3_io1 pc5 7 tsc_g7_io1 pe2 tsc_g3_io2 pb0 tsc_g7_io2 pe3 tsc_g3_io3 pb1 tsc_g7_io3 pe4 tsc_g3_io4 pb2 tsc_g7_io4 pe5 4 tsc_g4_io1 pa9 8 tsc_g8_io1 pd12 tsc_g4_io2 pa10 tsc_g8_io2 pd13 tsc_g4_io3 pa13 tsc_g8_io3 pd14 tsc_g4_io4 pa14 tsc_g8_io4 pd15 table 9. no. of capacitive sensing channels available on stm32f302xx/stm32f303xx devices analog i/o group number of capacitive sensing channels stm32f30xvx stm32f30xrx stm32f30xcx g1 3 3 3 g2 3 3 3 g3 3 3 2 g4 3 3 3 g5 3 3 3 g6 3 3 3 g7 3 0 0 g8 3 0 0 number of capacitive sensing channels 24 18 17 table 8. capacitive sensing gpios available on stm32f302xx/stm32f303xx devices (continued) group capacitive sensing signal name pin name group capacitive sensing signal name pin name http://
stm32f302xx/stm32f303xx functional overview doc id 023353 rev 5 31/133 stm32f302xx/stm32f303xx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using a high- speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. http://
pinouts and pin description stm32f302xx/stm32f303xx 32/133 doc id 023353 rev 5 4 pinouts and pin description figure 5. stm32f302xx/stm32f303xx lqfp48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 21 22 23 24 17 18 19 20 2 3 4 5 6 7 8 9 10 11 vbat pc14/osc32_in pc15/osc32_out nrst vssa/vref- vdda/vref+ pa0 pa1 pa2 vdd_1 vss_1 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 vdd_3 vss_3 pa13 pa12 pa11 pa10 pa 9 pa 8 pb15 pb14 pb13 pb12 pa 3 pa 4 pa 5 pa6 pa7 pb0 pb1 pb2 pb10 vss_2 pb11 vdd_2 pf0/osc_in pf1/osc_out pc13 12 1 .47 ,1&0 http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 33/133 figure 6. stm32f302xx/stm32f303xx lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14/osc32_in pc15/osc32_out nrst pc0 pc1 pc2 pc3 vssa/vref- vdda pa0 pa1 pa2 vdd_1 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 vdd_3 vss_3 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pf4 pa3 vdd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pf1/osc_out pf0/osc_in pc13 vss_1 pb11 vss_2 vdd_2 ,1&0 ai6 http://
pinouts and pin description stm32f302xx/stm32f303xx 34/133 doc id 023353 rev 5 figure 7. stm32f302xx/stm32f303xx lqfp100 pinout 0% 0% 0% 0% 0% 6"!4 0#/3#?). 0#/3#?/54 0& 0& 0&/3#?). .234 0# 0# 0# 0# 0& 633!62%& 62%& 6$$! 0! 0! 0! 6$$? 633? 0& 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 0& 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 633? 6$$? 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! ai6 ,1&0 0# 0&/3#?/54 0" http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 35/133 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers http://
pinouts and pin description stm32f302xx/stm32f303xx 36/133 doc id 023353 rev 5 table 11. stm32f302xx/stm32f303xx pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions 1 pe2 i/o ft (1) traceck, tim3_ch1, tsc_g7_io1 2 pe3 i/o ft (1) traced0, tim3_ch2, tsc_g7_io2 3 pe4 i/o ft (1) traced1, tim3_ch3, tsc_g7_io3 4 pe5 i/o ft (1) traced2, tim3_ch4, tsc_g7_io4 5 pe6 i/o ft (1) traced3 wkup3, rtc_tamp3 611 v bat s backup power supply 722pc13 (2) i/o tc tim1_ch1n wkup2, rtc_tamp1, rtc_ts, rtc_out 833 pc14 (2) osc32_in (pc14) i/o tc osc32_in 944 pc15 (2) osc32_ out (pc15) i/o tc osc32_out 10 pf9 i/o ft (1) tim15_ch1, spi2_sck 11 pf10 i/o ft (1) tim15_ch2, spi2_sck 12 5 5 pf0- osc_in (pf0) i/o ftf tim1_ch3n, i2c2_sda osc_in 13 6 6 pf1- osc_out (pf1) i/o ftf i2c2_scl osc_out 14 7 7 nrst i/o rst device reset input / internal reset output (active low) 15 8 pc0 i/o tta (1) adc12_in6, comp7_inm (3) 16 9 pc1 i/o tta (1) adc12_in7, comp7_inp (3) 17 10 pc2 i/o tta (1) comp7_out (3) adc12_in8 18 11 pc3 i/o tta (1) tim1_bkin2 adc12_in9 19 pf2 i/o tta (1) adc12_in10 20 12 8 vssa/ vref- s analog ground/negative reference voltage 21 vref+ s positive reference voltage 22 vdda s analog power supply 13 9 vdda/ vref+ s analog power supply/positive reference voltage http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 37/133 23 14 10 pa0 i/o tta usart2_cts, tim2_ch1_etr, tim8_bkin (3) , tim8_etr (3) , tsc_g1_io1, comp1_out adc1_in1, comp1_inm, rtc_ tamp2, wkup1, comp7_inp (3) 24 15 11 pa1 i/o tta usart2_rts, tim2_ch2, tsc_g1_io2, tim15_ch1n adc1_in2, comp1_inp, opamp1_vinp, opamp3_vinp (3) 25 16 12 pa2 i/o tta usart2_tx, tim2_ch3, tim15_ch1, tsc_g1_io3, comp2_out adc1_in3, comp2_inm, opamp1_vout 26 17 13 pa3 i/o tta usart2_rx, tim2_ch4, tim15_ch2, tsc_g1_io4 adc1_in4, opamp1_vinp, comp2_inp, opamp1_vinm 27 18 pf4 i/o tta (1) comp1_out adc1_in5 28 19 vdd_4 s 29 20 14 pa4 i/o tta spi1_nss, spi3_nss, i2s3_ws (3) , usart2_ck, tsc_g2_io1, tim3_ch2 adc2_in1, dac1_out1, opamp4_vinp (3) , comp1_inm, comp2_inm, comp3_inm (3) , comp4_inm, comp5_inm (3) , comp6_inm, comp7_inm (3) 30 21 15 pa5 i/o tta spi1_sck, tim2_ch1_etr, tsc_g2_io2 adc2_in2, dac1_out2 (3) opamp1_vinp, opamp2_vinm, opamp3_vinp (3) , comp1_inm, comp2_inm, comp3_inm (3) , comp4_inm, comp5_inm (3) , comp6_inm, comp7_inm (3) 31 22 16 pa6 i/o tta spi1_miso, tim3_ch1, tim8_bkin (3) , tim1_bkin, tim16_ch1, comp1_out, tsc_g2_io3 adc2_in3, opamp2_vout 32 23 17 pa7 i/o tta spi1_mosi, tim3_ch2, tim17_ch1, tim1_ch1n, tim8_ch1n (3) , tsc_g2_io4, comp2_out adc2_in4, comp2_inp, opamp2_vinp, opamp1_vinp 33 24 pc4 i/o tta (1) usart1_tx adc2_in5 34 25 pc5 i/o tta (1) usart1_rx, tsc_g3_io1 adc2_in11, opamp2_vinm, opamp1_vinm table 11. stm32f302xx/stm32f303xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions http://
pinouts and pin description stm32f302xx/stm32f303xx 38/133 doc id 023353 rev 5 35 26 18 pb0 i/o tta tim3_ch3, tim1_ch2n, tim8_ch2n (3) , tsc_g3_io2 adc3_in12 (3) , comp4_inp, opamp3_vinp (3) , opamp2_vinp 36 27 19 pb1 i/o tta tim3_ch4, tim1_ch3n, tim8_ch3n (3) , comp4_out, tsc_g3_io3 adc3_in1 (3) , opamp3_vout (3) 37 28 20 pb2 i/o tta tsc_g3_io4 adc2_in12, comp4_inm, opamp3_vinm (3) 38 pe7 i/o tta (1) tim1_etr adc3_in13 (3) , comp4_inp 39 pe8 i/o tta (1) tim1_ch1n comp4_inm, adc34_in6 (3) 40 pe9 i/o tta (1) tim1_ch1 adc3_in2 (3) 41 pe10 i/o tta (1) tim1_ch2n adc3_in14 (3) 42 pe11 i/o tta (1) tim1_ch2 adc3_in15 (3) 43 pe12 i/o tta (1) tim1_ch3n adc3_in16 (3) 44 pe13 i/o tta (1) tim1_ch3 adc3_in3 (3) 45 pe14 i/o tta (1) tim1_ch4, tim1_bkin2 adc4_in1 (3) 46 pe15 i/o tta (1) usart3_rx, tim1_bkin adc4_in2 (3) 47 29 21 pb10 i/o tta usart3_tx, tim2_ch3, tsc_sync comp5_inm (3) , opamp4_vinm (3) , opamp3_vinm (3) 48 30 22 pb11 i/o tta usart3_rx, tim2_ch4, tsc_g6_io1 comp6_inp, opamp4_vinp (3) 49 31 23 vss_2 s digital ground 50 32 24 vdd_2 s digital power supply 51 33 25 pb12 i/o tta spi2_nss, i2s2_ws (3) , i2c2_smba, usart3_ck, tim1_bkin, tsc_g6_io2 adc4_in3 (3) , comp3_inm (3) , opamp4_vout (3) , 52 34 26 pb13 i/o tta spi2_sck, i2s2_ck (3) , usart3_cts, tim1_ch1n, tsc_g6_io3 adc3_in5 (3) , comp5_inp (3) , opamp4_vinp (3) , opamp3_vinp (3) 53 35 27 pb14 i/o tta spi2_miso, i2s2ext_sd (3) , usart3_rts, tim1_ch2n, tim15_ch1, tsc_g6_io4 comp3_inp (3) , adc4_in4 (3) , opamp2_vinp 54 36 28 pb15 i/o tta spi2_mosi, i2s2_sd (3) , tim1_ch3n, tim15_ch1n, tim15_ch2 adc4_in5 (3) , rtc_refin, comp6_inm 55 pd8 i/o tta (1) usart3_tx adc4_in12 (3) , opamp4_vinm (3) 56 pd9 i/o tta (1) usart3_rx adc4_in13 (3) 57 pd10 i/o tta (1) usart3_ck adc34_in7 (3) , comp6_inm table 11. stm32f302xx/stm32f303xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 39/133 58 pd11 i/o tta (1) usart3_cts adc34_in8 (3) , comp6_inp, opamp4_vinp (3) 59 pd12 i/o tta (1) usart3_rts, tim4_ch1, tsc_g8_io1 adc34_in9 (3) , comp5_inp (3) 60 pd13 i/o tta (1) tim4_ch2, tsc_g8_io2 adc34_in10 (3) , comp5_inm (3) 61 pd14 i/o tta (1) tim4_ch3, tsc_g8_io3 comp3_inp (3) , adc34_in11 (3) , opamp2_vinp 62 pd15 i/o tta (1) spi2_nss, tim4_ch4, tsc_g8_io4 comp3_inm (3) 63 37 pc6 i/o ft (1) i2s2_mck (3) , comp6_out, tim8_ch1 (3) , tim3_ch1 64 38 pc7 i/o ft (1) i2s3_mck (3) , tim8_ch2 (3) , tim3_ch2, comp5_out (3) 65 39 pc8 i/o ft (1) tim8_ch3 (3) , tim3_ch3, comp3_out (3) 66 40 pc9 i/o ft (1) tim8_ch4 (3) , tim8_bkin2 (3) , tim3_ch4, i2s_ckin (3) 67 41 29 pa8 i/o ft i2c2_smba, i2s2_mck (3) , usart1_ck, tim1_ch1, tim4_etr, mco, comp3_out (3) 68 42 30 pa9 i/o ftf i2c2_scl, i2s3_mck (3) , usart1_tx, tim1_ch2, tim2_ch3, tim15_bkin, tsc_g4_io1, comp5_out (3) 69 43 31 pa10 i/o ftf i2c2_sda, usart1_rx, tim1_ch3, tim2_ch4, tim8_bkin (3) , tim17_bkin, tsc_g4_io2, comp6_out 70 44 32 pa11 i/o ft usart1_cts, usb_dm, can_rx, tim1_ch1n, tim1_ch4, tim1_bkin2, tim4_ch1, comp1_out 71 45 33 pa12 i/o ft usart1_rts, usb_dp, can_tx, tim1_ch2n, tim1_etr, tim4_ch2, tim16_ch1, comp2_out 72 46 34 pa13 i/o ft usart3_cts, tim4_ch3, tim16_ch1n, tsc_g4_io3, ir_out, swdio-jtms 73 pf6 i/o ftf (1) i2c2_scl, usart3_rts, tim4_ch4 table 11. stm32f302xx/stm32f303xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions http://
pinouts and pin description stm32f302xx/stm32f303xx 40/133 doc id 023353 rev 5 74 47 35 vss_3 s ground 75 48 36 vdd_3 s digital power supply 76 49 37 pa14 i/o ftf i2c1_sda, usart2_tx, tim8_ch2 (3) , tim1_bkin, tsc_g4_io4, swclk-jtck 77 50 38 pa15 i/o ftf i2c1_scl, spi1_nss, spi3_nss, i2s3_ws (3) , jtdi, usart2_rx, tim1_bkin, tim2_ch1_etr, tim8_ch1 (3) 78 51 pc10 i/o ft (1) spi3_sck, i2s3_ck (3) , usart3_tx, uart4_tx, tim8_ch1n (3) 79 52 pc11 i/o ft (1) spi3_miso, i2s3ext_sd (3) , usart3_rx, uart4_rx, tim8_ch2n (3) 80 53 pc12 i/o ft (1) spi3_mosi, i2s3_sd (3) , usart3_ck, uart5_tx, tim8_ch3n (3) 81 pd0 i/o ft (1) can_rx 82 pd1 i/o ft (1) can_tx, tim8_ch4 (3) , tim8_bkin2 (3) 83 54 pd2 i/o ft (1) uart5_rx, tim3_etr, tim8_bkin (3) 84 pd3 i/o ft (1) usart2_cts, tim2_ch1_etr 85 pd4 i/o ft (1) usart2_rts, tim2_ch2 86 pd5 i/o ft (1) usart2_tx 87 pd6 i/o ft (1) usart2_rx, tim2_ch4 88 pd7 i/o ft (1) usart2_ck, tim2_ch3 89 55 39 pb3 i/o ft spi3_sck, i2s3_ck (3) , spi1_sck, usart2_tx, tim2_ch2, tim3_etr, tim4_etr, tim8_ch1n (3) , tsc_g5_io1, jtdo- traceswo 90 56 40 pb4 i/o ft spi3_miso, i2s3ext_sd (3) , spi1_miso, usart2_rx, tim3_ch1, tim16_ch1, tim17_bkin, tim8_ch2n (3) , tsc_g5_io2, njtrst table 11. stm32f302xx/stm32f303xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 41/133 91 57 41 pb5 i/o ft spi3_mosi, spi1_mosi, i2s3_sd (3) , i2c1_smba, usart2_ck, tim16_bkin, tim3_ch2, tim8_ch3n (3) , tim17_ch1 92 58 42 pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n, tim4_ch1, tim8_ch1 (3) , tsc_g5_io3, tim8_etr (3) , tim8_bkin2 (3) 93 59 43 pb7 i/o ftf i2c1_sda, usart1_rx, tim3_ch4, tim4_ch2, tim17_ch1n, tim8_bkin (3) , tsc_g5_io4 94 60 44 boot0 i b boot memory selection 95 61 45 pb8 i/o ftf i2c1_scl, can_rx, tim16_ch1, tim4_ch3, tim8_ch2 (3) , tim1_bkin, tsc_sync, comp1_out 96 62 46 pb9 i/o ftf i2c1_sda, can_tx, tim17_ch1, tim4_ch4, tim8_ch3 (3) , ir_out, comp2_out 97 pe0 i/o ft (1) usart1_tx, tim4_etr, tim16_ch1 98 pe1 i/o ft (1) usart1_rx, tim17_ch1 99 63 47 vss_1 s ground 100 64 48 vdd_1 s digital power supply 1. function availability depends on the chosen device. when using the small packages (48 and 64 pin packages), the gpio pi ns which are not present on these packages, must not be configured in analog mode. 2. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch sinks only a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led). after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the main reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register des cription sections in the reference manual. 3. on stm32f303xx devices only. table 11. stm32f302xx/stm32f303xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions http://
pinouts and pin description stm32f302xx/stm32f303xx 42/133 doc id 023353 rev 5 table 12. alternate functions for port a port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af14 af15 pa 0 tim2_ ch1_ etr tsc_ g1_io1 usart2 _cts comp1 _out tim8_ bkin tim8_ etr event out pa 1 tim2_ ch2 tsc_ g1_io2 usart2 _rts tim15_ ch1n event out pa 2 tim2_ ch3 tsc_ g1_io3 usart2 _tx comp2 _out tim15_ ch1 event out pa 3 tim2_ ch4 tsc_ g1_io4 usart2 _rx tim15_ ch2 event out pa 4 tim3_ ch2 tsc_ g2_io1 spi1_ nss spi3_nss, i2s3_ws usart2 _ck event out pa 5 tim2_ ch1_ etr tsc_ g2_io2 spi1_ sck event out pa 6 tim16_ ch1 tim3_ ch1 tsc_ g2_io3 tim8_ bkin spi1_ miso tim1_bkin comp1 _out event out pa 7 tim17_ ch1 tim3_ ch2 tsc_ g2_io4 tim8_ ch1n spi1_ mosi tim1_ch1n comp2 _out event out pa 8 m c o i2c2_ smba i2s2_ mck tim1_ch1 usart1 _ck comp3 _out tim4_ etr event out pa 9 tsc_ g4_io1 i2c2_ scl i2s3_ mck tim1_ch2 usart1 _tx comp5 _out tim15_ bkin tim2_ ch3 event out pa 1 0 tim17_ bkin tsc_ g4_io2 i2c2_ sda tim1_ch3 usart1 _rx comp6 _out tim2_ ch4 tim8_ bkin event out pa11 tim1_ch1n usart1 _cts comp1 _out can_rx tim4_ ch1 tim1_ch4 tim1_ bkin2 usb_ dm event out http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 43/133 pa 1 2 tim16_ ch1 tim1_ch2n usart1 _rts comp2 _out can_tx tim4_ ch2 tim1_etr usb_ dp event out pa 1 3 swdio -jtms tim16_ ch1n tsc_ g4_io3 ir_ out usart3 _cts tim4_ ch3 event out pa 1 4 swclk -jtck tsc_ g4_io4 i2c1_ sda tim8_ ch2 tim1_bkin usart2 _tx event out pa 1 5 j t d i tim2_ ch1_ etr tim8_ ch1 i2c1_ scl spi1_ nss spi3_nss, i2s3_ws usart2 _rx tim1_ bkin event out table 12. alternate functions for port a (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af14 af15 http://
pinouts and pin description stm32f302xx/stm32f303xx 44/133 doc id 023353 rev 5 table 13. alternate functions for port b port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af12 af15 pb0 tim3_ ch3 tsc_ g3_io2 tim8_ ch2n tim1_ch2n event out pb1 tim3_ ch4 tsc_ g3_io3 tim8_ ch3n tim1_ch3n comp4_ out event out pb2 tsc_ g3_io4 event out pb3 jtdo- traces wo tim2_ ch2 tim4_ etr tsc_ g5_io1 tim8_ ch1n spi1_ sck spi3_sck, i2s3_ck usart2_ tx tim3_ etr event out pb4 njtrst tim16_ ch1 tim3_ ch1 tsc_ g5_io2 tim8_ ch2n spi1_ miso spi3_miso, i2s3ext_sd usart2_ rx tim17_ bkin event out pb5 tim16_ bkin tim3_ ch2 tim8_ ch3n i2c1_ smba spi1_ mosi spi3_mosi, i2s3_sd usart2_ ck tim17_ ch1 event out pb6 tim16_ ch1n tim4_ ch1 tsc_ g5_io3 i2c1_scl tim8_ch1 tim8_ etr usart1_ tx tim8_ bkin2 event out pb7 tim17_ ch1n tim4_ ch2 tsc_ g5_io4 i2c1_ sda tim8_ bkin usart1_ rx tim3_ ch4 event out pb8 tim16_ ch1 tim4_ ch3 tsc_ sync i2c1_scl comp1_ out can_rx tim8_ ch2 tim1_ bkin event out pb9 tim17_ ch1 tim4_ ch4 i2c1_ sda ir_out comp2_ out can_tx tim8_ ch3 event out pb10 tim2_ ch3 tsc_ sync usart3_ tx event out pb11 tim2_ ch4 tsc_ g6_io1 usart3_ rx event out pb12 tsc_ g6_io2 i2c2_ smba spi2_nss, i2s2_ws tim1_ bkin usart3_ ck event out http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 45/133 pb13 tsc_ g6_io3 spi2_sck, i2s2_ck tim1_ ch1n usart3_ cts event out pb14 tim15_ ch1 tsc_ g6_io4 spi2_miso, i2s2ext_sd tim1_ ch2n usart3_ rts event out pb15 tim15_ ch2 tim15_ ch1n tim1_ ch3n spi2_mosi, i2s2_sd event out table 13. alternate functions for port b (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af12 af15 http://
pinouts and pin description stm32f302xx/stm32f303xx 46/133 doc id 023353 rev 5 table 14. alternate functions for port c port & pin name af1 af2 af3 af4 af5 af6 af7 pc0 eventout pc1 eventout pc2 eventout comp7_out pc3 eventout tim1_bkin2 pc4 eventout usart1_tx pc5 eventout tsc_g3_io1 usart1_rx pc6 eventout tim3_ch1 tim 8_ch1 i2s2_mck comp6_out pc7 eventout tim3_ch2 tim 8_ch2 i2s3_mck comp5_out pc8 eventout tim3_ch3 tim8_ch3 comp3_out pc9 eventout tim3_ch4 tim8_ch4 i2s_ckin tim8_bkin2 pc10 eventout tim8_ch1n uart4_t x spi3_sck, i2s3_ck usart3_tx pc11 eventout tim8_ch2n uart4_rx spi 3_miso, i2s3ext_sd usart3_rx pc12 eventout tim8_ch3n uart5_tx spi3_mosi, i2s3_sd usart3_ck pc13 tim1_ch1n pc14 pc15 http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 47/133 table 15. alternate functions for port d port & pin name af1 af2 af3 af4 af5 af6 af7 pd0 eventout can_rx pd1 eventout tim8_ch4 tim8_bkin2 can_tx pd2 eventout tim3_etr tim8_bkin uart5_rx pd3 eventout tim2_ch1_etr usart2_cts pd4 eventout tim2_ch2 usart2_rts pd5 eventout usart2_tx pd6 eventout tim2_ch4 usart2_rx pd7 eventout tim2_ch3 usart2_ck pd8 eventout usart3_tx pd9 eventout usart3_rx pd10 eventout usart3_ck pd11 eventout usart3_cts pd12 eventout tim4_ch1 tsc_g8_io1 usart3_rts pd13 eventout tim4_ch2 tsc_g8_io2 pd14 eventout tim4_ch3 tsc_g8_io3 pd15 eventout tim4_ch4 tsc_g8_io4 spi2_nss http://
pinouts and pin description stm32f302xx/stm32f303xx 48/133 doc id 023353 rev 5 table 16. alternate functions for port e port & pin name af0 af1 af2 af3 af4 af6 af7 pe0 eventout tim4_etr tim16_ch1 usart1_tx pe1 eventout tim17_ch1 usart1_rx pe2 traceck eventout tim3_ch1 tsc_g7_io1 pe3 traced0 eventout tim3_ch2 tsc_g7_io2 pe4 traced1 eventout tim3_ch3 tsc_g7_io3 pe5 traced2 eventout tim3_ch4 tsc_g7_io4 pe6 traced3 eventout pe7 eventout tim1_etr pe8 eventout tim1_ch1n pe9 eventout tim1_ch1 pe10 eventout tim1_ch2n pe11 eventout tim1_ch2 pe12 eventout tim1_ch3n pe13 eventout tim1_ch3 pe14 eventout tim1_ch4 tim1_bkin2 pe15 eventout tim1_bkin usart3_rx http://
stm32f302xx/stm32f303xx pinouts and pin description doc id 023353 rev 5 49/133 table 17. alternate functions for port f port & pin name af1 af2 af3 af4 af5 af6 af7 pf0 i2c2_sda tim1_ch3n pf1 i2c2_scl pf2 eventout pf4 eventout comp1_out pf6 eventout tim4_ch4 i2c2_scl usart3_rts pf9 eventout tim15_ch1 spi2_sck pf10 eventout tim15_ch2 spi2_sck http://
memory mapping stm32f302xx/stm32f303xx 50/133 doc id 023353 rev 5 5 memory mapping figure 8. stm32f30xb/c memory map 0xffff ffff 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0 1 2 3 4 5 6 7 cortex-m4f internal peripherals peripherals sram code option bytes system memory flash memory flash, system memory or sram, depending on boot configuration ahb2 ahb1 apb2 apb1 0x5000 0000 0x4800 1800 0x4800 0000 0x4002 43ff 0x4002 0000 0x4001 6c00 0x4001 0000 0x4000 a000 0x4000 0000 0x1fff ffff 0x1fff f800 0x1fff d800 0x0804 0000 0x0800 0000 0x0004 0000 0x0000 0000 reserved ms30355v1 ahb3 0x5000 07ff reserved reserved reserved reserved reserved reserved reserved 0x1000 2000 0x1000 0000 ccm ram http://
stm32f302xx/stm32f303xx memory mapping doc id 023353 rev 5 51/133 table 18. stm32f30xb/c memory map and peripheral register boundary addresses bus boundary address size (bytes) peripheral ahb3 0x5000 0400 - 0x5000 07ff 1 k adc3 - adc4 0x5000 0000 - 0x5000 03ff 1 k adc1 - adc2 0x4800 1800 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k gpioe 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0800 - 0x4002 0fff 2 k reserved 0x4002 0400 - 0x4002 07ff 1 k dma2 0x4002 0000 - 0x4002 03ff 1 k dma1 0x4001 8000 - 0x4001 ffff 32 k reserved apb2 0x4001 4c00 - 0x4001 7fff 13 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k reserved 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3400 - 0x4001 37ff 1 k tim8 0x4001 3000 - 0x4001 33ff 1 k spi1 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 9 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + opamp http://
memory mapping stm32f302xx/stm32f303xx 52/133 doc id 023353 rev 5 0x4000 8000 - 0x4000 ffff 32 k reserved apb1 0x4000 7800 - 0x4000 7fff 2 k reserved 0x4000 7400 - 0x4000 77ff 1 k dac (dual) 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 6c00 - 0x4000 6fff 1 k reserved 0x4000 6800 - 0x4000 6bff 1 k reserved 0x4000 6400 - 0x4000 67ff 1 k bxcan 0x4000 6000 - 0x4000 63ff 1 k usb sram 512 bytes 0x4000 5c00 - 0x4000 5fff 1 k usb device fs 0x4000 5800 - 0x4000 5bff 1 k i2c2 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 5000 - 0x4000 53ff 1 k uart5 0x4000 4c00 - 0x4000 4fff 1 k uart4 0x4000 4800 - 0x4000 4bff 1 k usart3 0x4000 4400 - 0x4000 47ff 1 k usart2 0x4000 4000 - 0x4000 43ff 1 k i2s3ext 0x4000 3c00 - 0x4000 3fff 1 k spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 k spi2/i2s2 0x4000 3400 - 0x4000 37ff 1 k i2s2ext 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k rtc 0x4000 1800 - 0x4000 27ff 4 k reserved 0x4000 1400 - 0x4000 17ff 1 k tim7 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0c00 - 0x4000 0fff 1 k reserved 0x4000 0800 - 0x4000 0bff 1 k tim4 0x4000 0400 - 0x4000 07ff 1 k tim3 0x4000 0000 - 0x4000 03ff 1 k tim2 table 18. stm32f30xb/c memory map and peripheral register boundary addresses (continued) bus boundary address size (bytes) peripheral http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 53/133 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 9. pin loading condition s figure 10. pin input voltage -36 c = 50 pf -#5pin -36 -#5pin 6 ). http://
electrical characteristics stm32f302xx/stm32f303xx 54/133 doc id 023353 rev 5 6.1.6 power supply scheme figure 11. power supply scheme 1. dotted lines represent the inter nal connections on low pin count pa ckages, joining the dedicated supply pins. caution: each power supply pair (v dd /v ss , v dda /v ssa etc..) must be decoupled with filtering ceramic capacitors as shown above. these capac itors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. ms19875v3 po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (lse,rtc, backup registers) wake-up logic 100 nf + 1 4.7 f 1.65 - 3.6v regulator v dda v ssa adc/ dac level shifter io logic v dd 10 nf + 1 f v dda v ref+ v ref- v dd v ss 4 3 v ref 10 nf + 1 f 4 !nalog2#s0,, comparators/0!-0 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 55/133 6.1.7 current con sumption measurement figure 12. current consumption measurement scheme -36 6 "!4 6 $$ 6 $$! ) $$ ?6 "!4 ) $$ ) $$! http://
electrical characteristics stm32f302xx/stm32f303xx 56/133 doc id 023353 rev 5 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 19: voltage characteristics , table 20: current characteristics , and table 21: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 19. voltage characteristics (1) symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda, v bat and v dd ) -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4 v ref+ ?v dda (2) allowed voltage difference for v ref+ > v dda -0.4 v in (3) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. the following relati onship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . 2. v ref+ must be always lower or equal than v dda (v ref+ v dda) . if unused then it must be connected to v dda . 3. v in maximum must always be respected. refer to table 20: current characteristics for the maximum allowed injected current values. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 57/133 table 20. current characteristics symbol ratings max. unit i vdd( ) total current into sum of all vdd_x power lines (source) 160 ma i vss( ) total current out of sum of all vss_x ground lines (sink) ? 160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) ? 100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin ? 25 i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) ? 80 i inj(pin) injected current on ft, ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correc tly distributed over all i/os and control pi ns.the total output current must not be sunk/sourced between two consecut ive power supply pins referring to high pin count lqfp packages 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dd while a negative injection is induced by v in v dda while a negative injection is induced by v in electrical characteristics stm32f302xx/stm32f303xx 58/133 doc id 023353 rev 5 6.3 operating conditions 6.3.1 general operating conditions table 22. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda analog operating voltage (opamp and dac not used) must have a potential equal to or higher than v dd 23.6 v analog operating voltage (opamp and dac used) 2.4 3.6 v bat backup operating voltage 1.65 3.6 v v in i/o input voltage tc i/o ?0.3 v dd +0.3 v tta i/o ?0.3 v dda +0.3 ft and ftf i/o (1) 1. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pul l-down resistors must be disabled. ?0.3 5.5 boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see table 21: thermal characteristics ). lqfp100 - 488 mw lqfp64 - 444 lqfp48 - 364 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (3) 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see table 21: thermal characteristics ). ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 59/133 6.3.2 operating conditions at power-up / power-down the parameters given in ta bl e 2 3 are derived from tests performed under the ambient temperature condition summarized in ta b l e 2 2 . 6.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 2 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 2 2 . table 23. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20 t vdda v dda rise time rate 0 v dda fall time rate 20 table 24. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the opti on bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - 40 - mv t rsttempo (3) 3. guaranteed by design, not tested in production por reset temporization 1.5 2.5 4.5 ms http://
electrical characteristics stm32f302xx/stm32f303xx 60/133 doc id 023353 rev 5 6.3.4 embedded reference voltage the parameters given in ta bl e 2 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 2 2 . table 25. programmable voltage detector characteristics symbol parameter conditions min (1) 1. data based on characterization results only, not tested in production. typ max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 falling edge 2.09 2.18 2.27 v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 falling edge 2.18 2.28 2.38 v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 falling edge 2.28 2.38 2.48 v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 falling edge 2.37 2.48 2.59 v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 falling edge 2.47 2.58 2.69 v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 falling edge 2.56 2.68 2.8 v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 falling edge 2.66 2.78 2.9 v pvdhyst (2) 2. guaranteed by design, not tested in production. pvd hysteresis - 100 - mv idd(pvd) pvd current consumption - 0.15 0.26 a table 26. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) v t s_vrefint adc sampling time when reading the internal reference voltage 2.2 - - s v rerint internal reference voltage spread over the temperature range v dd = 3 v 10 mv - - 10 (2) mv t coeff temperature coefficient - - 100 (2) ppm/c http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 61/133 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 12: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in ta bl e 2 8 to ta bl e 3 2 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . 1. data based on characterization results, not tested in production. 2. guaranteed by design, not tested in production table 27. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb http://
electrical characteristics stm32f302xx/stm32f303xx 62/133 doc id 023353 rev 5 table 28. typical and maximum current consumption from v dd supply at v dd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 61.2 65.8 67.6 68.5 27.8 30.3 30.7 31.5 ma 64 mhz 54.7 59.1 60.2 61.1 24.6 27.2 27.6 28.3 48 mhz 41.7 45.1 46.2 47.2 19.2 21.1 21.4 21.8 32 mhz 28.1 31.5 32.5 32.7 12.9 14.6 14.8 15.3 24 mhz 21.4 23.7 24.4 25.2 10.0 11.4 11.4 12.1 8 mhz 7.4 8.4 8.6 9.4 3.6 4.1 4.4 5.0 1 mhz 1.3 1.6 1.8 2.6 0.8 1.0 1.2 2.1 internal clock (hsi) 64 mhz 49.7 54.4 55.4 56.3 24.5 27.2 27.4 28.1 48 mhz 37.9 42.2 43.0 43.5 18.9 21.4 21.5 21.6 32 mhz 25.8 29.2 29.2 30.0 12.7 14.2 14.6 15.2 24 mhz 19.7 22.3 22.6 23.2 6.7 7.7 7.9 8.5 8 mhz 6.9 7.8 8.3 8.8 3.5 4.0 4.4 5.0 supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 60.8 66.2 (2) 69.7 70.4 (2) 27.4 31.7 (2) 32.2 32.5 (2) 64 mhz 54.3 59.1 62.2 63.3 24.3 28.3 28.7 28.8 48 mhz 41.0 45.6 47.3 47.9 18.3 21.6 21.9 22.1 32 mhz 27.6 32.4 32.4 32.9 12.3 15.0 15.2 15.4 24 mhz 20.8 23.9 24.3 25.0 9.3 11.3 11.4 12.0 8 mhz 6.9 7.8 8.7 9.0 3.1 3.7 4.2 4.9 1 mhz 0.9 1.2 1.5 2.3 0.4 0.6 1.0 1.8 internal clock (hsi) 64 mhz 49.2 53.9 55.2 57.4 23.9 27.8 28.2 28.4 48 mhz 37.3 40.8 41.4 44.1 18.2 21.0 21.6 21.9 32 mhz 25.1 27.6 29.1 30.1 12.0 14.0 14.5 15.1 24 mhz 19.0 21.6 22.1 22.9 6.3 7.2 7.7 8.1 8 mhz 6.4 7.3 7.9 8.4 3.0 3.5 4.0 4.7 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 63/133 i dd supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 44.0 48.4 49.4 50.5 6.6 7.5 7.9 8.7 ma 64 mhz 39.2 43.3 44.0 45.2 6.0 6.8 7.2 7.9 48 mhz 29.6 32.7 33.3 34.3 4.5 5.2 5.6 6.3 32 mhz 19.7 23.3 23.3 23.5 3.1 3.5 4.0 4.8 24 mhz 14.9 17.6 17.8 18.3 2.4 2.8 3.3 3.9 8 mhz 4.9 5.7 6.1 6.9 0.8 1.0 1.4 2.2 1 mhz 0.6 0.9 1.2 2.1 0.1 0.3 0.6 1.5 internal clock (hsi) 64 mhz 34.2 38.1 39.2 40.3 5.7 6.3 6.8 7.5 48 mhz 25.8 28.7 29.6 30.3 4.3 4.8 5.2 5.9 32 mhz 17.4 19.4 19.9 20.7 2.9 3.2 3.7 4.5 24 mhz 13.2 15.1 15.6 15.9 1.5 1.8 2.2 2.9 8 mhz 4.5 5.0 5.6 6.2 0.7 0.9 1.2 2.1 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and test ed in production with c ode executing from ram. table 28. typical and maximum current consumption from v dd supply at v dd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c table 29. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run mode, code executing from flash or ram hse bypass 72 mhz 225 276 289 297 245 302 319 329 a 64 mhz 198 249 261 268 216 270 284 293 48 mhz 149 195 204 211 159 209 222 230 32 mhz 102 145 152 157 110 154 162 169 24 mhz 80 119 124 128 86 126 131 135 8 mhz23463459 1 mhz23573469 hsi clock 64 mhz 270 323 337 344 299 354 371 381 48 mhz 220 269 280 286 244 293 309 318 32 mhz 173 218 228 233 193 239 251 257 24 mhz 151 194 200 204 169 211 219 225 8 mhz 73 97 99 103 88 105 110 116 http://
electrical characteristics stm32f302xx/stm32f303xx 64/133 doc id 023353 rev 5 1. current consumption from the v dda supply is independent of whether the perip herals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 65/133 table 30. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd =v dda )max (1) unit 2.0v 2.4v 2.7v 3.0 v 3.3v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 20.05 20.33 20.42 20.50 20.67 20.80 44.2 (2) 553 1202 (2) a regulator in low-power mode, all oscillators off 7.63 7.77 7.90 8.07 8.17 8.33 30.6 (2) 529 1156 (2) supply current in standby mode lsi on and iwdg on 0.80 0.96 1.09 1.23 1.37 1.51 - - - lsi off and iwdg off 0.60 0.74 0.83 0.93 1.02 1.11 5.0 (2) 7.8 13.3 (2) 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production. table 31. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda monitoring on regulator in run mode, all oscillators off 1.81 1.95 2.07 2.20 2.35 2.52 3.7 5.5 8.8 a regulator in low-power mode, all oscillators off 1.81 1.95 2.07 2.20 2.35 2.52 3.7 5.5 8.8 supply current in standby mode lsi on and iwdg on 2.22 2.42 2.59 2.78 3.0 3.24 - - - lsi off and iwdg off 1.69 1.82 1.94 2.08 2.23 2.40 3.5 5.4 9.2 supply current in stop mode v dda monitoring off regulator in run mode, all oscillators off 1.05 1.08 1.10 1.15 1.22 1.29 - - - regulator in low-power mode, all oscillators off 1.05 1.08 1.10 1.15 1.22 1.29 - - - supply current in standby mode lsi on and iwdg on 1.44 1.52 1.60 1.71 1.84 1.98 - - - lsi off and iwdg off 0.93 0.95 0.98 1.02 1.08 1.15 - - - 1. data based on characterization results, not tested in production. http://
electrical characteristics stm32f302xx/stm32f303xx 66/133 doc id 023353 rev 5 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) table 32. typical and maximum current consumption from v bat supply symbol para meter conditions (1) typ @v bat max @v bat = 3.6 v (2) unit 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v t a = 25c t a = 85c t a = 105c i dd_vbat backup domain supply current lse & rtc on; "xtal mode" lower driving capability; lsedrv[1: 0] = '00' 0.48 0.50 0.52 0.58 0.65 0.72 0.80 0.90 1.1 1.5 2.0 a lse & rtc on; "xtal mode" higher driving capability; lsedrv[1: 0] = '11' 0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5 2.2 2.9 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. data based on characterization results, not tested in production. ?# ?# ?# ?# 6 6 6 6 6 6 6 6 4 ! ?# ?! ) 6"!4 -36 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 67/133 typical current consumption the mcu is placed under the following conditions: v dd = v dda = 3.3 v all i/o pins available on each package are in analog input configuration the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb pll is used for frequencies greater than 8 mhz ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. table 33. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 61.3 28.0 ma 64 mhz 54.8 25.4 48 mhz 41.9 19.3 32 mhz 28.5 13.3 24 mhz 21.8 10.4 16 mhz 14.9 7.2 8 mhz 7.7 3.9 4 mhz 4.5 2.5 2 mhz 2.8 1.7 1 mhz 1.9 1.3 500 khz 1.4 1.1 125 khz 1.1 0.9 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 240.3 239.5 a 64 mhz 210.9 210.3 48 mhz 155.8 155.6 32 mhz 105.7 105.6 24 mhz 82.1 82.0 16 mhz 58.8 58.8 8 mhz 2.4 2.4 4 mhz 2.4 2.4 2 mhz 2.4 2.4 1 mhz 2.4 2.4 500 khz 2.4 2.4 125 khz 2.4 2.4 1. v dda monitoring is on. http://
electrical characteristics stm32f302xx/stm32f303xx 68/133 doc id 023353 rev 5 2. when peripherals are enabled, the power c onsumption of the analog part of peripher als such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. table 34. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 44.1 7.0 ma 64 mhz 39.7 6.3 48 mhz 30.3 4.9 32 mhz 20.5 3.5 24 mhz 15.4 2.8 16 mhz 10.6 2.0 8 mhz 5.4 1.1 4 mhz 3.2 1.0 2 mhz 2.1 0.9 1 mhz 1.5 0.8 500 khz 1.2 0.8 125 khz 1.0 0.8 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 239.7 238.5 a 64 mhz 210.5 209.6 48 mhz 155.0 155.6 32 mhz 105.3 105.2 24 mhz 81.9 81.8 16 mhz 58.7 58.6 8 mhz 2.4 2.4 4 mhz 2.4 2.4 2 mhz 2.4 2.4 1 mhz 2.4 2.4 500 khz 2.4 2.4 125 khz 2.4 2.4 1. v dda monitoring is on 2. when peripherals are enabled, the power c onsumption of the analog part of peripher als such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 69/133 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 52: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext +c s the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = http://
electrical characteristics stm32f302xx/stm32f303xx 70/133 doc id 023353 rev 5 table 35. switching output i/o current consumption symbol parameter conditions (1) i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.90 ma 4 mhz 0.93 8 mhz 1.16 18 mhz 1.60 36 mhz 2.51 48 mhz 2.97 v dd = 3.3 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.93 4 mhz 1.06 8 mhz 1.47 18 mhz 2.26 36 mhz 3.39 48 mhz 5.99 v dd = 3.3 v c ext = 22 pf c = c int + c ext +c s 2 mhz 1.03 4 mhz 1.30 8 mhz 1.79 18 mhz 3.01 36 mhz 5.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.10 4 mhz 1.31 8 mhz 2.06 18 mhz 3.47 36 mhz 8.35 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.20 4 mhz 1.54 8 mhz 2.46 18 mhz 4.51 36 mhz 9.98 1. cs = 5 pf (estimated value). http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 71/133 on-chip peripheral current consumption the mcu is placed under the following conditions: all i/o pins are in analog input configuration all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature at 25c and v dd = v dda = 3.3 v. table 36. peripheral current consumption peripheral typical consumption (1) unit i dd busmatrix (2) 5.6 a/mhz dma1 15.3 dma2 12.5 crc 2.1 gpioa 10.0 gpiob 10.3 gpioc 2.2 gpiod 8.8 gpioe 3.3 gpiof 3.0 tsc 5.5 adc1&2 17.3 adc3&4 18.8 apb2-bridge (3) 3.6 syscfg 7.3 tim1 40.0 spi1 8.8 tim8 36.4 usart1 23.3 tim15 17.1 tim16 10.1 tim17 11.0 apb1-bridge (3) 6.1 tim2 49.1 tim3 38.8 tim4 38.3 http://
electrical characteristics stm32f302xx/stm32f303xx 72/133 doc id 023353 rev 5 tim6 9.7 a/mhz tim7 12.1 wwdg 6.4 spi2 40.4 spi3 40.0 usart2 41.9 usart3 40.2 uart4 36.5 uart5 30.8 i2c1 10.5 i2c2 10.4 usb 26.2 can 33.4 pwr 5.7 dac 15.4 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. 2. busmatrix is automatically active when at least one master is on (cpu, dma1 or dma2). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. table 36. peripheral current consumption (continued) peripheral typical consumption (1) unit i dd http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 73/133 6.3.6 wakeup time from low-power mode the wakeup times given in ta bl e 3 7 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: for stop or sleep mode: the wakeup event is wfe. wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . table 37. low-power mode wakeup timings symbol parameter conditions typ @v dd, v dd = v dda max unit 2.0 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v t wustop wakeup from stop mode regulator in run mode 4.1 3.9 3.8 3.7 3.6 3.5 4.5 s regulator in low power mode 7.9 6.7 6.1 5.7 5.4 5.2 9 t wustandby (1) wakeup from standby mode lsi and iwdg off 69.2 60.3 56.4 53.7 51.7 50 100 t wusleep wakeup from sleep mode 6- cpu clock cycles 1. data based on characterization results, not tested in production. http://
electrical characteristics stm32f302xx/stm32f303xx 74/133 doc id 023353 rev 5 6.3.7 external cloc k source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to resp ect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 14 . figure 14. high-speed external clock source ac timing diagram table 38. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 -36 6 (3%( t f(3% 4 (3% t t r(3% 6 (3%, t 7(3%( t 7(3%, http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 75/133 low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to resp ect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 15 figure 15. low-speed external clock source ac timing diagram table 39. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 -36 6 ,3%( t f,3% 4 ,3% t t r,3% 6 ,3%, t 7,3%( t 7,3%, http://
electrical characteristics stm32f302xx/stm32f303xx 76/133 doc id 023353 rev 5 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typi cal external components specified in ta b l e 4 0 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 40. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. min (2) 2. guaranteed by design, not tested in production. typ max (2) unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time --8.5 ma v dd =3.3 v, rm= 30 , cl=10 pf@8 mhz -0.4- v dd =3.3 v, rm= 45 , cl=10 pf@8 mhz -0.5- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -0.8- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -1- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 77/133 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the app lication note an 2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 16. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. -36 /3#?/5 4 /3#?). f (3% # , 2 & -( z resonator 2 %84 # , 2esonatorwith integratedcapacitors "ias controlled gain http://
electrical characteristics stm32f302xx/stm32f303xx 78/133 doc id 023353 rev 5 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typi cal external components specified in ta b l e 4 1 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the app lication note an 2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 41. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]=01 medium low driving capability --1 lsedrv[1:0]=10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]=01 medium low driving capability 8- - lsedrv[1:0]=10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enab led (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly wi th the crystal manufacturer http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 79/133 figure 17. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. /3#?/5 4 /3#?). f ,3% # , k( z resonator # , 2esonatorwith integratedcapacitors $rive programmable amplifier http://
electrical characteristics stm32f302xx/stm32f303xx 80/133 doc id 023353 rev 5 6.3.8 internal clock source characteristics the parameters given in ta bl e 4 2 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . high-speed internal (hsi) rc oscillator figure 18. hsi oscillator accuracy characterization results 1. the above curves are based on characterisa tion results, not tested in production table 42. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 - mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. -4.6 (3) % t a = ?10 to 85 c ?2.9 (3) -2.9 (3) % t a = 0 to 70 c - - - % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dd(hsi) hsi oscillator power consumption - 80 100 (3) a -36 -!8 -). 4!;?#= !## (3) http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 81/133 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in ta bl e 4 4 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . table 43. lsi oscillator characteristics (1) 1. v dda = 3.3 v , t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 44. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -72mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design, not tested in production. ps http://
electrical characteristics stm32f302xx/stm32f303xx 82/133 doc id 023353 rev 5 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 45. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 46. flash memory endurance and data retention symbol parameter conditions value unit min (1) n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 30 ye a r s 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 1. data based on characterization results, not tested in production. 2. cycling performed over t he whole temperature range. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 83/133 6.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 4 7 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 47. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-4 4a http://
electrical characteristics stm32f302xx/stm32f303xx 84/133 doc id 023353 rev 5 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sensi tivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 48. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 7 dbv 30 to 130 mhz 20 130 mhz to 1ghz 27 sae emi level 4 - table 49. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii 500 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 85/133 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the test results are given in ta b l e 5 1 table 50. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a http://
electrical characteristics stm32f302xx/stm32f303xx 86/133 doc id 023353 rev 5 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 51. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ? 0 na ma injected current on pc0, pc1, pc2, pc3, pf2, pa0, pa 1 , pa 2 , pa 3 , p f 4 , pa 4 , pa 5 , pa 6 , pa 7 , p c 4 , p c 5 , pb2 with induced leakage current on other pins from this group less than -50 a ? 5 - injected current on pb0, pb1, pe7, pe8, pe9, pe10, pe11, pe12, pe13, pe14, pe15, pb12, pb13, pb14, pb15, pd8, pd9, pd10, pd 11, pd12, pd13, pd14 with induced leakage current on other pins from this group less than -50 a ? 5 - injected current on pc0, pc1, pc2, pc3, pf2, pa0, pa 1 , pa 2 , pa 3 , p f 4 , pa 4 , pa 5 , pa 6 , pa 7 , p c 4 , p c 5 , pb2, pb0, pb1, pe7, pe8, pe 9, pe10, pe11, pe12, pe13, pe14, pe15, pb12, pb13, pb14, pb15, pd8, pd9, pd10, pd11, pd12, pd13, pd14 with induced leakage current on other pins from this group less than 400 a -+5 injected current on any other ft and ftf pins ? 5 na injected current on any other pins ? 5 +5 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 87/133 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 5 2 are derived from tests performed under the conditions summarized in ta b l e 2 2 . all i/os are cmos and ttl compliant. table 52. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tc and tta i/o 0.445 v dd +0.398 (1) -- ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft and ftf i/o tta i/o in digital mode v ss v in v dd --0.1 a tta i/o in digital mode v dd v in v dda --1 tta i/o in analog mode v ss v in v dda --0.2 ft and ftf i/o (4) v dd v in 5v --10 r pu weak pull-up equivalent resistor (5) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (5) v in = v dd 25 40 55 k c io i/o pin capacitance - 5 - pf 1. data based on design simulation. 2. tested in production. 3. leakage could be higher than the maximum value. if negat ive current is injected on adjacent pins. refer to table 51: i/o current injection susceptibility . 4. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull- down resistors must be disabled. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). http://
electrical characteristics stm32f302xx/stm32f303xx 88/133 doc id 023353 rev 5 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 19 and figure 20 for standard i/os. figure 19. tc and tta i/o input characteristics - cmos port figure 20. tc and tta i/o input characteristics - ttl port figure 21. five volt tolerant (ft and ftf) i/o input characteristics - cmos port ms30255v2 v dd (v) v ihmin 2.0 v ilmax 0.7 v il /v ih (v) 1.3 2.0 3.6 v ilmax = 0.3v dd +0.07 0.6 2.7 3.0 3.3 cmos standard requirements v ilmax = 0.3v dd v ihmin = 0.445v dd +0.398 area not determined tested in production tested in production based on design simulations based on design simulations cmos standard requirements v ihmin = 0.7 v dd ms30256v2 v dd (v) v ihmin 2.0 v ilmax 0.8 v il /v ih (v) 1.3 2.0 3.6 ttl standard requirements v ihmin = 2 v v ilmax = 0.3v dd +0.07 0.7 2.7 3.0 3.3 ttl standard requirements v ilmax = 0.8 v v ihmin = 0.445v dd +0.398 area not determined based on design simulations based on design simulations ms30257v2 v dd (v) 2.0 v il /v ih (v) 1.0 2.0 3.6 v ilmax = 0.475v dd -0.2 0.5 cmos standard requirements v ilmax = 0.3v dd v ihmin = 0.5v dd +0.2 area not determined based on design simulations based on design simulations tested in production cmos standard requirements v ihmin = 0.7 v dd tested in production http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 89/133 figure 22. five volt tolerant (ft and ftf) i/o input characteristics - ttl port ms30258v2 v dd (v) 2.0 v il /v ih (v) 1.0 2.0 3.6 v ilmin = 0.475v dd -0.2 0.5 v ihmin = 0.5v dd +0.2 area not determined 2.7 ttl standard requirements v ihmin = 2 v ttl standard requirements v ilmax = 0.8 v 0.8 based on design simulations based on design simulations http://
electrical characteristics stm32f302xx/stm32f303xx 90/133 doc id 023353 rev 5 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 6.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd( ) (see ta b l e 2 0 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss( ) (see ta bl e 2 0 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 5 3 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. table 53. output voltage characteristics symbol parameter con ditions min max unit v ol (1) output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4 1. the i io current sunk by the device mu st always respect the absolut e maximum rating specified in table 20 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. the i io current sourced by the device must always res pect the absolute maximum rating specified in table 20 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 4. data based on design simulation. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 91/133 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 23 and ta bl e 5 4 , respectively. unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . table 54. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -125 (3) ns t r(io)out output low to high level rise time -125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 (3) mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 (3) mhz c l = 50 pf, v dd = 2 v to 2.7 v - 20 (3) mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v -2 (4) mhz t f(io)out output high to low level fall time -12 (4) ns t r(io)out output low to high level rise time -34 (4) -t extipw pulse width of external signals detected by the exti controller 10 (3) -ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the rm0316 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 23 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypas sed in fm+ i/o mode. refer to the st m32f30xb/c reference manual rm0316 for a description of fm+ i/o mode configuration. http://
electrical characteristics stm32f302xx/stm32f303xx 92/133 doc id 023353 rev 5 figure 23. i/o ac characteristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 5 2 ). unless otherwise specified, the parameters given in ta bl e 5 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 55. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse 500 - - ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 93/133 figure 24. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 55 . otherwise the reset will not be taken into account by the device. 6.3.16 timer characteristics the parameters given in ta bl e 5 6 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). -36 2 05 .234 6 $$ &ilter )nternal2eset ?& %xternal resetcircuit symbol parameter conditions min typ max unit v il(npor) (1) 1. guaranteed by design, not tested in production. npor input low level voltage 0.475v dda - 0.2 v v ih(npor) (1) npor input high level voltage 0.5v dda + 0.2 v hys(npor) (1) npor schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order). v in = v ss 25 40 55 k table 56. timx (1) characteristics symbol parameter conditions min max unit t res(tim) (2) timer resolution time 1- t timxclk f timxclk = 72 mhz (except tim1/8) 13.9 - ns f timxclk = 144 mhz, x= 1.8 6.95 - ns f ext (2) timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim (2) timer resolution timx (except tim2) - 16 bit tim2 - 32 http://
electrical characteristics stm32f302xx/stm32f303xx 94/133 doc id 023353 rev 5 t counter (2) 16-bit counter clock period 1 65536 t timxclk f timxclk = 72 mhz (except tim1/8) 0.0139 910 s f timxclk = 144 mhz, x= 1.8 0.0069 455 s t max_count (2) maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 72 mhz - 59.65 s f timxclk = 144 mhz, x= 1.8 - 29.825 s 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim4, tim8, tim15, tim16 and tim17 timers 2. guaranteed by design, not tested in production. table 56. timx (1) characteristics (continued) symbol parameter conditions min max unit http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 95/133 table 57. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the mi crocontroller?s internal rc frequency can va ry from 30 to 60 khz. moreover, given an exac t rc oscillator frequency, the exac t timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout (ms) rl[11:0]= 0x000 max timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 58. wwdg min-max timeout value @72 mhz (pclk) prescaler wdgtb min timeout value max timeout value 1 0 0.05687 (1) 1. guaranteed by design, not tested in production. 3.6409 (1) 2 1 0.1137 (1) 7.2817 (1) 4 2 0.2275 (1) 14.564 (1) 8 3 0.4551 (1) 29.127 (1) http://
electrical characteristics stm32f302xx/stm32f303xx 96/133 doc id 023353 rev 5 6.3.17 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 5 9 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 2 2 . the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 5 9 . refer also to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 59. i 2 c characteristics (1) symbol parameter standard mode fast mode fast mode plus unit min max min max min max t w(scll) scl clock low time 4.7 - 1.3 - 0.5 - s t w(sclh) scl clock high time 4.0 - 0.6 - 0.26 - t su(sda) sda setup time 250 - 100 - 50 - ns t h(sda) sda data hold time 0 (3) 3450 (2) 0 (3) 900 (2) 0 450 t r(sda) t r(scl) sda and scl rise time - 1000 - 300 - 120 t f(sda) t f(scl) sda and scl fall time - 300 - 300 - 120 t h(sta) start condition hold time 4.0 - 0.6 - 0.26 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - 0.26 - t su(sto) stop condition setup time 4.0 - 0.6 - 0.26 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - 0.5 - s c b capacitive load for each bus line - 400 - 400 - 550 pf 1. the i2c characteristics are the requirements from i2c bus specification rev03. they are guaranteed by design when i2cx_timing register is correctly progr ammed (refer to reference manual). th ese characteristics are not tested in production. 2. the maximum data hold time has only to be met if the in terface does not stretch the low period of scl signal. 3. the device must internally pr ovide a hold time of at least 300ns for the sd a signal in order to br idge the undefined region of the falling edge of scl. table 60. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t sp pulse width of spikes that are suppressed by the analog filter 50 260 ns http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 97/133 figure 25. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . -36 34!24 3$ ! ) #bus 2 6 $$ 6 $$ -#5 3$! 3#, t f3$! t r3$! 3#, t h34! t w3#,( t w3#,, t su3$! t r3#, t f3#, t h3$! 3 4!242%0%!4%$ 34!24 t su34! t su34/ 34/0 t w34/34! 2 http://
electrical characteristics stm32f302xx/stm32f303xx 98/133 doc id 023353 rev 5 spi/i 2 s characteristics unless otherwise specified, the parameters given in ta bl e 6 1 for spi or in ta bl e 6 2 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 2 2 . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 61. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) (1) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) (1) spi clock rise and fall time capacitive load: c = 30 pf - 8 ns ducy(sck) (1) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. data based on characterization results, not tested in production. nss setup time slave mode 2tpclk - ns t h(nss) (1) nss hold time slave mode 4tpclk - t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 - 3 tpclk/2 + 3 t su(mi) (1) t su(si) (1) data input setup time master mode 5.5 - slave mode 6.5 - t h(mi) (1) data input hold time master mode 5 - t h(si) (1) slave mode 5 - t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 24 mhz 0 4tpclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. data output disable time slave mode 0 24 t v(so) (1) data output valid time slave mode (after enable edge) - 39 t v(mo) (1) data output valid time master mode (after enable edge) - 3 t h(so) (1) data output hold time slave mode (after enable edge) 15 - t h(mo) (1) master mode (after enable edge) 4 - http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 99/133 figure 26. spi timing diagram - slave mode and cpha = 0 figure 27. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input http://
electrical characteristics stm32f302xx/stm32f303xx 100/133 doc id 023353 rev 5 figure 28. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. ai6 3#+/utput #0(! -/3) /54054 -)3/ ).0 54 #0(! -3 "). - 3"/54 ") 4). ,3"/54 ,3"). #0/, #0/, " ) 4/54 .33input t c3#+ t w3#+( t w3#+, t r3#+ t f3#+ t h-) (igh 3#+/utput #0(! #0(! #0/, #0/, t su-) t v-/ t h-/ table 62. i 2 s characteristics symbol parameter conditions min max unit f ck 1/t c(ck) (1) i 2 s clock frequency master data: 16 bits, audio freq=48 khz 1.496 1.503 mhz slave 0 12.288 t r(ck) t f(ck) (1) i 2 s clock rise and fall time capacitive load c l =30pf -8 ns t w(ckh) (1) i 2 s clock high time master f pclk = 36 mhz, audio frequency = 48 khz 331 - t w(ckl) (1) i 2 s clock low time 332 - t v(ws) (1) ws valid time master mode 4 - t h(ws) (1) ws hold time master mode 4 - t su(ws) (1) ws setup time slave mode 4 - t h(ws) (1) ws hold time slave mode 0 - duty cycle (1) i 2 s slave input clock duty cycle slave mode 30 70 % http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 101/133 figure 29. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. t su(sd_mr) (1) data input setup ti me master receiver 9 ns t su(sd_sr) (1) data input setup ti me slave receiver 2 t h(sd_mr) (1) data input hold time master receiver 0 t h(sd_sr) (1) slave receiver 0 t v(sd_st) (1) data output valid time slave transmitter (after enable edge) 29 t h(sd_st) (1) data output hold time slave transmitter (after enable edge) 12 t v(sd_mt) (1) data output valid time master transmitter (after enable edge) 3 t h(sd_mt) (1) data output hold time master transmitter (after enable edge) 2 1. data based on characterization results, not tested in production. table 62. i 2 s characteristics (continued) symbol parameter conditions min max unit ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) http://
electrical characteristics stm32f302xx/stm32f303xx 102/133 doc id 023353 rev 5 figure 30. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. usb characteristics ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) table 63. usb startup time symbol parameter max unit t startup (1) usb transceiver startup time 1 s 1. guaranteed by design, not tested in production. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 103/133 figure 31. usb timings: definition of data signal rise and fall time table 64. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 full-speed electrical specification, the usb_dp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f3xxx usb functionality is ensured down to 2.7 v but not the fu ll usb electrical characteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by design, not tested in production. differential input sensitivity i(usb_dp, usb_dm) 0.2 - v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers -0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 ai14137 t f differen tial data l ines v ss v cr s t r crossover points http://
electrical characteristics stm32f302xx/stm32f303xx 104/133 doc id 023353 rev 5 can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 65. usb: full-speed electrical characteristics (1) symbol parameter conditions min typ max unit driver characteristics t r rise time (2) c l = 50 pf 4 - 20 ns t f fall time (2) c l = 50 pf 4 - 20 ns t rfm rise/ fall time matching t r /t f 90 - 110 % v crs output signal crossover voltage 1.3 - 2.0 v output driver impedance (3) z drv driving high and low 28 40 44 1. guaranteed by design, not tested in production. 2. measured from 10% to 90% of the data signal. for more detail ed informations, please refer to usb specification - chapter 7 (version 2.0). 3. no external termination series resi stors are required on usb_dp (d+) and u sb_dm (d-), the matching impedance is already included in the embedded driver. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 105/133 6.3.18 adc characteristics unless otherwise specified, the parameters given in ta b l e 6 6 to ta bl e 6 9 are guaranteed by design, with conditio ns summarized in ta bl e 2 2 . table 66. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc 2-3.6v f adc adc clock frequency 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits - - 5.14 mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range 0 - v dda v r ain (1) external input impedance - - 100 k c adc (1) internal sample and hold capacitor -5-pf t cal (1) calibration time f adc = 72 mhz 1.56 s 112 1/f adc t latr (1) trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 11 - - 2.125 1/f adc t latrinj (1) trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 11 - - 3.125 1/f adc t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s 1.5 - 601.5 1/f adc tadcvreg _stup (1) adc voltage regulator start-up time - - 10 s t conv (1) total conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 3.5 s resolution = 12 bits 14 to 252 (t s for sampling + 12.5 for successive approximation) 1/f adc 1. data guaranteed by design http://
electrical characteristics stm32f302xx/stm32f303xx 106/133 doc id 023353 rev 5 table 67. maximum adc r ain resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (1) slow channels other channels (2) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. all fast channels, expect channels on pa2, pa6, pb1, pb12. 2. channels available on pa2, pa6, pb1 and pb12. http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 107/133 table 68. adc accuracy - limited test conditions (1)(2) symbol parameter conditions min (3) typ max (3) unit et to t a l unadjusted error adc clock freq. 72 mhz sampling freq 5 msps v dda = v ref+ = 3.3 v 25c single ended fast channel 5.1 ms - 3.5 6 lsb slow channel 4.8 ms - 4.5 7 differential fast channel 5.1 ms - 3.5 6 slow channel 4.8 ms - 3.5 6 eo offset error single ended fast channel 5.1 ms - 1 5 slow channel 4.8 ms - 1 5 differential fast channel 5.1 ms - 1 3 slow channel 4.8 ms - 1 3 eg gain error single ended fast channel 5.1 ms - 3 6 slow channel 4.8 ms - 4 6 differential fast channel 5.1 ms - 1 2 slow channel 4.8 ms - 1.5 3 ed differential linearity error single ended fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1.5 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 3 slow channel 4.8 ms - 2 3 differential fast channel 5.1 ms - 1 2 slow channel 4.8 ms - 1 2 enob effective number of bits single ended fast channel 5.1 ms 10.3 10.7 - bits slow channel 4.8 ms 10.4 10.7 - differential fast channel 5.1 ms 10.9 11.3 - slow channel 4.8 ms 10.9 11.3 - sinad signal-to- noise and distortion ratio single ended fast channel 5.1 ms 64 66 - db slow channel 4.8 ms 65 66 - differential fast channel 5.1 ms 67 70 - slow channel 4.8 ms 67 70 - http://
electrical characteristics stm32f302xx/stm32f303xx 108/133 doc id 023353 rev 5 snr signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = v ref+ = 3.3 v 25c single ended fast channel 5.1 ms 64 67 - db slow channel 4.8 ms 65 67 - differential fast channel 5.1 ms 68 70 - slow channel 4.8 ms 69 70 - thd to t a l harmonic distortion single ended fast channel 5.1 ms - ? 75 ? 72 slow channel 4.8 ms - ? 72 ? 70 differential fast channel 5.1 ms - ? 80 ? 74 slow channel 4.8 ms - ? 76 ? 71 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection curre nt: injecting negative current on any anal og input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. data based on characterization results, not tested in production. table 68. adc accuracy - limited test conditions (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 109/133 table 69. adc accuracy (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to t a l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 2v v dda , v ref+ 3.6 v single ended fast channel 5.1 ms - 7 lsb slow channel 4.8 ms - 7 differential fast channel 5.1 ms - 7 slow channel 4.8 ms - 7 eo offset error single ended fast channel 5.1 ms - 5 slow channel 4.8 ms - 5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4 eg gain error single ended fast channel 5.1 ms - 7 slow channel 4.8 ms - 7 differential fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2 enob effective number of bits single ended fast channel 5.1 ms 10.2 - bits slow channel 4.8 ms 10.2 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - http://
electrical characteristics stm32f302xx/stm32f303xx 110/133 doc id 023353 rev 5 figure 32. adc accuracy characteristics sinad signal-to- noise and distortion ratio adc clock freq. 72 mhz, sampling freq. 5 msps, 2v v dda , v ref+ 3.6 v single ended fast channel 5.1 ms - 63 db slow channel 4.8 ms - 63 differential fast channel 5.1 ms - 67 slow channel 4.8 ms - 67 snr signal-to- noise ratio single ended fast channel 5.1 ms 64 - slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd to t a l harmonic distortion single ended fast channel 5.1 ms - ? 71 slow channel 4.8 ms - ? 69 differential fast channel 5.1 ms - ? 73 slow channel 4.8 ms - ? 70 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative cu rrent on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. table 69. adc accuracy (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 111/133 figure 33. typical connection diagram using the adc 1. refer to ta b l e 6 6 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 11 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. -36 6 $$! ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc 12-bit converter c adc sample and hold adc converter http://
electrical characteristics stm32f302xx/stm32f303xx 112/133 doc id 023353 rev 5 6.3.19 dac elect rical specifications table 70. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage for dac on 2.4 - 3.6 v r load (1) resistive load with buffer on 5 - - k r o (1) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off --v dda ? 1lsb v i dda (3) dac dc current consumption in quiescent mode (standby mode) (2) -- 380 a with no load, middle code (0x800) on the input -- 480 a with no load, worst code (0xf1c) on the input dnl (3) differential non linearity difference between two consecutive code-1lsb) - - 0.5 lsb given for a 10-bit input code - - 2 lsb given for a 12-bit input code inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) - - 1 lsb given for a 10-bit input code - - 4 lsb given for a 12-bit input code offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) -- 10mv -- 3lsb given for a 10-bit input code at v dda = 3.6 v -- 12lsb given for a 12-bit input code at v dda = 3.6 v gain error (3) gain error - - 0.5 % given for a 12-bit input code http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 113/133 figure 34. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb -3 4 sc load 50 pf, r load 5 k update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/sc load 50 pf, r load 5 k t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement - ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac a keeping steady value on the output, so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. table 70. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 http://
electrical characteristics stm32f302xx/stm32f303xx 114/133 doc id 023353 rev 5 6.3.20 comparator characteristics table 71. comparator characteristics symbol parameter conditions min (1) typ max (1) unit v dda analog supply voltage 2 - 3.6 v v in comparator input voltage range 0-v dda v bg scaler input voltage - 1.2 - v sc scaler offset voltage - 5 10 mv t s_sc scaler startup time from power down --0.1ms t start comparator startup time startup time to reach propagation delay specification --60s t d propagation delay for 200 mv step with 100 mv overdrive ultra-low power mode - 2 4.5 s low power mode - 0.7 1.5 medium power mode - 0.3 0.6 high speed mode v dda 2.7 v - 50 100 ns v dda < 2.7 v - 100 240 propagation delay for full range step with 100 mv overdrive ultra-low power mode - 2 7 s low power mode - 0.7 2.1 medium power mode - 0.3 1.2 high speed mode v dda 2.7 v - 90 180 ns v dda < 2.7 v - 110 300 v offset comparator offset error - 4 10 mv dv offset /dt offset error temperature coefficient -18- v/ c i dd(comp) comp current consumption ultra-low power mode - 1.2 1.5 a low power mode - 3 5 medium power mode - 10 15 high speed mode - 75 100 http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 115/133 v hys comparator hysteresis no hysteresis (compxhyst[1:0]=00) -0- mv low hysteresis (compxhyst[1:0]=01) high speed mode 3 8 13 all other power modes 510 medium hysteresis (compxhyst[1:0]=10) high speed mode 7 15 26 all other power modes 919 high hysteresis (compxhyst[1:0]=11) high speed mode 18 31 49 all other power modes 19 40 1. data based on characterization results, not tested in production. table 71. comparator characteristics (continued) symbol parameter conditions min (1) typ max (1) unit http://
electrical characteristics stm32f302xx/stm32f303xx 116/133 doc id 023353 rev 5 6.3.21 operational am plifier char acteristics table 72. operational amplifier characteristics (1) symbol parameter condition min typ max unit v dda analog supply voltage 2.4 - 3.6 v cmir common mode input range 0 - v dda v vi offset input offset voltage maximum calibration range 25c, no load on output. --4 mv all voltage/temp. --6 after offset calibration 25c, no load on output. --1.6 all voltage/temp. --3 vi offset input offset voltage drift - 5 - v/c i load drive current - - 500 a iddopamp consumption no load, quiescent mode - 690 1450 a cmrr common mode rejection ratio - 90 - db psrr power supply rejection ratio dc 73 117 - db gbw bandwidth - 8.2 - mhz sr slew rate - 4.7 - v/s r load resistive load 4 - - k c load capacitive load - - 50 pf voh sat high saturation voltage r load = min, input at v dda . - - 100 mv r load = 20k, input at v dda . --20 vol sat low saturation voltage rload = min, input at 0v - - 100 rload = 20k, input at 0v. --20 ? m phase margin - 62 - t offtrim offset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy --2ms t wakeup wake up time from off state. c load 50 pf, r load 4 k , follower configuration -2.85s http://
stm32f302xx/stm32f303xx electrical characteristics doc id 023353 rev 5 117/133 pga gain non inverting gain value -2- -4- -8- -16- r network r2/r1 internal resistance values in pga mode (2) gain=2 - 5.4/5.4 - k gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error -1% - 1% i bias opamp input bias current - - 0.2 (3) a 1. data guaranteed by design. 2. r2 is the internal resistance betw een opamp output and opamp inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 3. mostly tta i/o leakage, when used in analog mode. table 72. operational amplifier characteristics (1) symbol parameter condition min typ max unit http://
electrical characteristics stm32f302xx/stm32f303xx 118/133 doc id 023353 rev 5 6.3.22 temperature sen sor characteristics 6.3.23 v bat monitoring characteristics table 73. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s table 74. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 75. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 2.2 - - s http://
stm32f302xx/stm32f303xx package characteristics doc id 023353 rev 5 119/133 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. http://
package characteristics stm32f302xx/stm32f303xx 120/133 doc id 023353 rev 5 figure 35. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b ! table 76. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 15.80 16.00 16.2 0.622 0.6299 0.6378 d1 13.80 14.00 14.2 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.2 0.622 0.6299 0.6378 http://
stm32f302xx/stm32f303xx package characteristics doc id 023353 rev 5 121/133 figure 36. recommended footprint 1. dimensions are in millimeters. e1 13.80 14.00 14.2 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 76. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 75 51 50 76 0.5 0. 3 16.7 14. 3 100 26 12. 3 25 1.2 16.7 1 a i14906 b http://
package characteristics stm32f302xx/stm32f303xx 122/133 doc id 023353 rev 5 figure 37. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline 1. drawing is not to scale. ! ! ! 3%!4).' 0,!.% ccc # b # c ! , , + '!5'%0,!.% mm )$%.4)&)#!4)/. 0). $ $ $ e % % % 7?-%?6 table 77. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 11.80 12.00 12.20 0.4646 0.4724 0.4803 d1 9.80 10.00 10.20 0.3858 0.3937 0.4016 d3 7.50 0.2953 http://
stm32f302xx/stm32f303xx package characteristics doc id 023353 rev 5 123/133 figure 38. recommended footprint 1. dimensions are in millimeters. e 11.80 12.00 12.20 0.4646 0.4724 0.4803 e1 9.80 10.00 10.20 0.3858 0.3937 0.4016 e3 7.50 0.2953 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 77. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aib http://
package characteristics stm32f302xx/stm32f303xx 124/133 doc id 023353 rev 5 figure 39. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. "?-%?6 0). )$%.4)&)#!4)/. ccc # # $ mm '!5'%0,!.% b ! ! ! c ! , , $ $ % % % e 3%!4).' 0,!.% + table 78. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 8.80 9.00 9.20 0.3465 0.3543 0.3622 d1 6.80 7.00 7.20 0.2677 0.2756 0.2835 d3 5.50 0.2165 e 8.80 9.00 9.20 0.3465 0.3543 0.3622 e1 6.80 7.00 7.20 0.2677 0.2756 0.2835 e3 5.50 0.2165 e 0.50 0.0197 http://
stm32f302xx/stm32f303xx package characteristics doc id 023353 rev 5 125/133 figure 40. recommended footprint 1. dimensions are in millimeters. l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 78. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aid http://
package characteristics stm32f302xx/stm32f303xx 126/133 doc id 023353 rev 5 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 22: general operating conditions on page 58 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org table 79. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 41 http://
stm32f302xx/stm32f303xx package characteristics doc id 023353 rev 5 127/133 7.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f30xb/c at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be be st suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 3 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 2 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 3 8 ma 0.4 v + 2 20 ma 1.3 v = 61.6 mw this gives: p intmax = 175 mw and p iomax = 61.6 mw: p dmax = 175 + 61.6 = 236.6 mw thus: p dmax = 236.6 mw using the values obtained in ta b l e 7 9 t jmax is calculated as follows: ? for lqfp64, 45c/w t jmax = 82 c + (45c/w 236.6 mw) = 82 c + 10.65 c = 92.65 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see section 8: part numbering ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 9 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 9 8 ma 0.4 v = 28.8 mw this gives: p intmax = 70 mw and p iomax = 28.8 mw: p dmax = 70 + 28.8 = 98.8 mw thus: p dmax = 98.8 mw http://
package characteristics stm32f302xx/stm32f303xx 128/133 doc id 023353 rev 5 using the values obtained in ta b l e 7 9 t jmax is calculated as follows: ? for lqfp100, 41c/w t jmax = 115 c + (41c/w 98.8 mw) = 115 c + 4.05 c = 119.05 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see section 8: part numbering ). http://
stm32f302xx/stm32f303xx part numbering doc id 023353 rev 5 129/133 8 part numbering table 80. ordering information scheme example: stm32 f 303 r b t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 302 = stm32f302xx 303 = stm32f303xx pin count c = 48 pins r = 64 pins v = 100 pins flash memory size b = 128 kbytes of flash memory (medium density) c = 256 kbytes of flash memory (high density) package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and reel http://
revision history stm32f302xx/stm32f303xx 130/133 doc id 023353 rev 5 9 revision history table 81. document revision history date revision changes 22-jun-2012 1 initial release 07-sep-2012 2 modified features on cover page. modified table 2: stm32f301xx family device features and peripheral counts added clock tree to section 3.8: clocks and startup added table 5: stm32f30xb/c i2c implementation added table 6: usart features added table 7: stm32f30xb/c spi/i2s implementation modified table 8: capacitive sensing gpios available on stm32f302xx/stm32f303xx devices modified figure 5 , figure 6 and figure 7: stm32f302xx/stm32f303xx lqfp100 pinout modified table 11: stm32f302xx/stm32f303xx pin definitions modified figure 11: power supply scheme modified table 19: voltage characteristics modified table 20: current characteristics modified table 23: operating conditions at power-up / power-down added footnote to table 29: typical and maximum current consumption from the vdda supply added footnote to ta b l e 3 3 and table 34: typical current consumption in sleep mode, code running from flash or ram removed table ?switching output i/o current consumption? and table ?peripheral current consumption? added note under figure 17: typical application with a 32.768 khz crystal updated table 42: hsi oscillator characteristics updated wakeup time from low-power mode and table 37: low-power mode wakeup timings updated table 45: flash memory characteristics updated table 50: electrical sensitivities updated table 51: i/o current injection susceptibility updated table 52: i/o static characteristics updated table 53: output voltage characteristics updated table 55: nrst pin characteristics updated table 61: spi characteristics updated table 62: i2s characteristics corrected lqfp100 in section 7.2.3: selecting the product temperature range 21-sep-2012 3 updated table 61: spi characteristics http://
stm32f302xx/stm32f303xx revision history doc id 023353 rev 5 131/133 05-dec-2012 4 updated first page removed references to vddsdx and vsssd added reference to pm0214 in section 1 moved temp. sensor calibartion values to ta b l e 7 4 and vref calibration values to ta bl e 2 7 updated table 2: stm32f30xb/c family device features and peripheral counts on page 10 updated section 3.4: embedded sram on page 14 updated section 3.2: memory protection unit (mpu) on page 13 updated section 3.23: universal serial bus (usb) on page 28 modified section 3.25: touch sensing controller (tsc) on page 29 updated heading of table 6: usart features on page 27 updated table 11: stm32f302xx/stm32f303xx pin definitions on page 36 added notes to pc13, pc14 and pc15 in table 11: stm32f302xx/stm32f303xx pin definitions on page 36 updated figure 11: power supply scheme on page 54 modified table 19: voltage characteristics on page 56 modified table 20: current characteristics on page 57 modified table 22: general operating conditions on page 58 modified figure 13: typical vbat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) on page 66 updated section 6.3.14: i/o port characteristics on page 87 updated table 28: typical and maximum current consumption from vdd supply at vdd = 3.6v on page 62 and table 29: typical and maximum current consumption from the vdda supply on page 63 updated table 30: typical and maximum vdd consumption in stop and standby modes on page 65 and ta b l e 3 1 : ty p i c a l a n d m a x i m u m vdda consumption in stop and standby modes on page 65 updated table 32: typical and maximum current consumption from vbat supply on page 66 added figure 13: typical vbat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) updated table 33: typical current consumption in run mode, code with data processing running from flash on page 67 and table 34: typical current consumption in sleep mode, code running from flash or ram on page 68 added table 36: peripheral current consumption on page 71 added table 35: switching output i/o current consumption on page 70 updated section 6.3.6: wakeup time from low-power mode on page 73 modified esd absolute maximum ratings on page 84 modified table 53: output voltage characteristics on page 90 updated emi characteristics on page 84 updated table 54: i/o ac characteristics on page 91 updated table 51: i/o current injection susceptibility on page 86 updated table 56: timx characteristics on page 93 updated section 7.2: thermal characteristics on page 126 added table 67: maximum adc rain on page 106 added table 68: adc accuracy - limited test conditions on page 107 updated table 69: adc accuracy on page 109 updated table 70: dac characteristics on page 112 updated table 72: operational amplifier characteristics on page 116 updated figures and tables in section 7: package characteristics table 81. document revision history date revision changes http://
revision history stm32f302xx/stm32f303xx 132/133 doc id 023353 rev 5 08-jan-2013 5 updated v hys and i lkg in table 52: i/o static characteristics . updated v il(nrst) , v ih(nrst) , and v nf(nrst) in table 55: nrst pin characteristics . updated table 68: adc accuracy - limited test conditions and ta b l e 6 9 : adc accuracy . table 81. document revision history date revision changes http://
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